Webinar
DVClub Europe
Agenda (BST): Time Session Description Slides Videos 12.00 BST 16:30 IST Welcome and Introduction Mike Bartley, Senior Vice President… Read More »DVClub Europe
Cadence TECHTALK: Mixed-Signal SoC Verification Simplified with Xcelium Simulator (NA)
Analog and mixed-signal verification has always been a challenge for design and verification engineers. It has become tedious with the increasing complexity of SoC designs. Join this webinar to learn… Read More »Cadence TECHTALK: Mixed-Signal SoC Verification Simplified with Xcelium Simulator (NA)
Pre-empt Late-stage Low Power Issues using Predictive Analysis
Low power is an increasingly critical requirement for all modern SoCs. Moreover, it is becoming more and more difficult with complex architectures being used in modern designs. This has made it necessary for designers to… Read More »Pre-empt Late-stage Low Power Issues using Predictive Analysis
Designing with Silvaco’s Octal SPI Memory Controller with Advanced Memory Support for IoT Systems
Abstract One commonality across semiconductor market segments is the need for memory. However, memory characteristics and interfaces vary greatly depending on the market segment and application. This webinar will focus on a… Read More »Designing with Silvaco’s Octal SPI Memory Controller with Advanced Memory Support for IoT Systems
Analog Waveform Viewing with Schematic Cross-Probing
Debugging takes a significant proportion of any engineer’s time, and there is much that can be done to improve individual and team’s productivity in this area. Using SpiceVison PRO and… Read More »Analog Waveform Viewing with Schematic Cross-Probing
UVM for FPGAs (Part 1)
Presenter: Srinivasan Venkataramanan, Entrepreneur and Head of VerifWorks Thursday, September 9, 2021 Abstract: The Accelera Universal Verification Methodology (UVM) became an IEEE standard published as IEEE 1800.2 – IEEE Standard… Read More »UVM for FPGAs (Part 1)
Improving Initial RTL Quality
Development projects, whether FPGA or ASIC SoCs or IP, run into late surprises that quickly result in schedule slips, expensive rework, and/or difficult feature cuts. It is possible to find… Read More »Improving Initial RTL Quality
How Synopsys Interface IP and Arm Interoperate to Accelerate System IO and Memory Performance
In this webinar, Synopsys and Arm describe how their recent collaboration helps maximize system performance and shorten Arm-based SoC design cycles. Learn how to minimize HPC/data center SoC design risk… Read More »How Synopsys Interface IP and Arm Interoperate to Accelerate System IO and Memory Performance
Automatic Generation of SystemVerilog Models from Analog/Mixed-Signal Circuits: a Pipelined ADC Example
When verifying large SoC designs, one needs to write SystemVerilog models for analog/mixed-signal blocks to comply with the digital verification flow, such as UVM. This talk addresses ways to extract… Read More »Automatic Generation of SystemVerilog Models from Analog/Mixed-Signal Circuits: a Pipelined ADC Example
How to Improve Your Chip Design Performance and Productivity Using Machine Learning
New applications and technology are driving demand for even more compute power and functionality in the devices we use every day. This has resulted in the semiconductor industry experiencing strong… Read More »How to Improve Your Chip Design Performance and Productivity Using Machine Learning
Benefits of a Common Methodology for Emulation and Prototyping
Overview Many design teams have used some form of hardware verification throughout their verification cycle for years now. Some engineering teams prefer to use emulation, some prefer to use prototyping,… Read More »Benefits of a Common Methodology for Emulation and Prototyping
UVM for FPGAs (Part 2): Solving FPGA Verification Challenges with UVM
Abstract: Today’s FPGAs have become larger in logic density and can handle complex designs with multi-million system logic cells. The traditional verification techniques of simple simulations combined with a detailed… Read More »UVM for FPGAs (Part 2): Solving FPGA Verification Challenges with UVM