Webinar
Calendar of Events
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1 event,
DVClub Europe
DVClub Europe
Agenda (BST): Time Session Description Slides Videos 12.00 BST 16:30 IST Welcome and Introduction Mike Bartley, Senior Vice President – VLSI Design, Tessolve 12.05 BST 16:35 IST I’m Excited About Formal…My Journey From Skeptic To Believer Neil Johnson, Senior Product Engineering Manager, Siemens EDA… Read More »DVClub Europe
2 events,
Cadence TECHTALK: Mixed-Signal SoC Verification Simplified with Xcelium Simulator (NA)
Cadence TECHTALK: Mixed-Signal SoC Verification Simplified with Xcelium Simulator (NA)
Analog and mixed-signal verification has always been a challenge for design and verification engineers. It has become tedious with the increasing complexity of SoC designs. Join this webinar to learn how Cadence is providing effective verification and debug methodologies using RNM of analog blocks for mixed-signal SoC verification.
Pre-empt Late-stage Low Power Issues using Predictive Analysis
Pre-empt Late-stage Low Power Issues using Predictive Analysis
Low power is an increasingly critical requirement for all modern SoCs. Moreover, it is becoming more and more difficult with complex architectures being used in modern designs. This has made it necessary for designers to invest heavily in this verification effort throughout the design development cycle starting from architecture definition, RTL development, to final netlist tape-out. Conventionally, static low power flow constitutes defining and cleaning… Read More »Pre-empt Late-stage Low Power Issues using Predictive Analysis
3 events,
Analog Waveform Viewing with Schematic Cross-Probing
Analog Waveform Viewing with Schematic Cross-Probing
Debugging takes a significant proportion of any engineer’s time, and there is much that can be done to improve individual and team’s productivity in this area. Using SpiceVison PRO and it’s analog waveform capabilities, users can perform post-processing functionalities and perform various measurements. Make SpiceVision PRO your unified platform for viewing and debugging analog circuits.… Read More »Analog Waveform Viewing with Schematic Cross-Probing
Designing with Silvaco’s Octal SPI Memory Controller with Advanced Memory Support for IoT Systems
Designing with Silvaco’s Octal SPI Memory Controller with Advanced Memory Support for IoT Systems
Abstract One commonality across semiconductor market segments is the need for memory. However, memory characteristics and interfaces vary greatly depending on the market segment and application. This webinar will focus on a specific class of memory devices – targeted to mobile and IoT applications – that use “SPI” (Serial Peripheral Interface) signaling. SPI was developed by Motorola… Read More »Designing with Silvaco’s Octal SPI Memory Controller with Advanced Memory Support for IoT Systems
UVM for FPGAs (Part 1)
UVM for FPGAs (Part 1)
Presenter: Srinivasan Venkataramanan, Entrepreneur and Head of VerifWorks Thursday, September 9, 2021 Abstract: The Accelera Universal Verification Methodology (UVM) became an IEEE standard published as IEEE 1800.2 – IEEE Standard for UVM Language Reference Manual (LRM). UVM has been the predominant verification methodology for ASIC designs for many years and has recently gained popularity and… Read More »UVM for FPGAs (Part 1)
3 events,
Improving Initial RTL Quality
Improving Initial RTL Quality
Development projects, whether FPGA or ASIC SoCs or IP, run into late surprises that quickly result in schedule slips, expensive rework, and/or difficult feature cuts. It is possible to find entire classes of issues without waiting for a testbench. This webinar will introduce you to a testbench-free designer-driven verification flow, resulting in a lower cost… Read More »Improving Initial RTL Quality
How Synopsys Interface IP and Arm Interoperate to Accelerate System IO and Memory Performance
How Synopsys Interface IP and Arm Interoperate to Accelerate System IO and Memory Performance
In this webinar, Synopsys and Arm describe how their recent collaboration helps maximize system performance and shorten Arm-based SoC design cycles. Learn how to minimize HPC/data center SoC design risk and ensure end-to-end IP integration, using available Arm reference designs and interoperability reports. Find out how Synopsys’ interface IP for the most widely used protocols… Read More »How Synopsys Interface IP and Arm Interoperate to Accelerate System IO and Memory Performance
Automatic Generation of SystemVerilog Models from Analog/Mixed-Signal Circuits: a Pipelined ADC Example
Automatic Generation of SystemVerilog Models from Analog/Mixed-Signal Circuits: a Pipelined ADC Example
When verifying large SoC designs, one needs to write SystemVerilog models for analog/mixed-signal blocks to comply with the digital verification flow, such as UVM. This talk addresses ways to extract those models automatically from circuits. The first approach is called structural modeling, mapping each device in the circuit to an equivalent model in SystemVerilog and… Read More »Automatic Generation of SystemVerilog Models from Analog/Mixed-Signal Circuits: a Pipelined ADC Example
3 events,
How to Improve Your Chip Design Performance and Productivity Using Machine Learning
How to Improve Your Chip Design Performance and Productivity Using Machine Learning
New applications and technology are driving demand for even more compute power and functionality in the devices we use every day. This has resulted in the semiconductor industry experiencing strong growth based on technology like 5G, autonomous driving, hyperscale compute, industrial IoT, and many others. System-on-chip (SoC) designs are quickly migrating to new process nodes… Read More »How to Improve Your Chip Design Performance and Productivity Using Machine Learning
Benefits of a Common Methodology for Emulation and Prototyping
Benefits of a Common Methodology for Emulation and Prototyping
Overview Many design teams have used some form of hardware verification throughout their verification cycle for years now. Some engineering teams prefer to use emulation, some prefer to use prototyping, and some even use both. Why would engineering teams invest in both platforms? Join our experts to understand why you should consider bridging emulation and… Read More »Benefits of a Common Methodology for Emulation and Prototyping
UVM for FPGAs (Part 2): Solving FPGA Verification Challenges with UVM
UVM for FPGAs (Part 2): Solving FPGA Verification Challenges with UVM
Abstract: Today’s FPGAs have become larger in logic density and can handle complex designs with multi-million system logic cells. The traditional verification techniques of simple simulations combined with a detailed validation in the lab simply do not scale up any longer. Even to map a large logic design to a modern-day FPGA takes many hours.… Read More »UVM for FPGAs (Part 2): Solving FPGA Verification Challenges with UVM
3 events,
A Novel Reversible Scan Chain Technology that Improves Chain Diagnosis Resolution by 4X
A Novel Reversible Scan Chain Technology that Improves Chain Diagnosis Resolution by 4X
If you can’t make the live session, please register anyway and you’ll get the link to the recorded session afterward. The complicated silicon defect types and defect distribution for advanced technologies can lead to initially very low yield for new design with new technology. To ramp up yield as quickly as possible to meet the market window,… Read More »A Novel Reversible Scan Chain Technology that Improves Chain Diagnosis Resolution by 4X
Learn About SiCure – Silvaco’s New IR Drop and Thermal Analysis Solution
Learn About SiCure – Silvaco’s New IR Drop and Thermal Analysis Solution
Learn About SiCure – Silvaco’s New IR Drop and Thermal Analysis Solution Silvaco introduces SiCure, an exciting new development tool for IR-drop and thermal analysis. While being very accurate, SiCure is an extremely intuitive and easy to use tool requiring minimal data input. Now it is easier than ever to find layout issues that will… Read More »Learn About SiCure – Silvaco’s New IR Drop and Thermal Analysis Solution
UVM for FPGAs (Part 3): Verifying Zynq MPSoC Designs?
UVM for FPGAs (Part 3): Verifying Zynq MPSoC Designs?
Learn how UVM Register Access Layer (RAL) can help Presenter: Srinivasan Venkataramanan, Entrepreneur and Head of VerifWorks Thursday, September 23, 2021 Abstract: The use of highly configurable IP-based designs have become the norm in the SoC era. Modern SoC designs targeting Xilinx® Zynq Ultrascale+ MPSoC include an extensive list of standard embedded IPs and custom… Read More »UVM for FPGAs (Part 3): Verifying Zynq MPSoC Designs?
2 events,
Formal 101 – Exhaustive Scoreboarding and Data Integrity Verification Made Easy
Formal 101 – Exhaustive Scoreboarding and Data Integrity Verification Made Easy
Verifying the correct passage of data through a DUT in constrained-random simulation is easy to do for basic I/O cases – data loss, obvious corruption, and 1-1 data passage. But what about verifying out-of-order cases? Or intermittently dropped bytes? Granted, a testbench can be written to look out for these issues, but as the layers… Read More »Formal 101 – Exhaustive Scoreboarding and Data Integrity Verification Made Easy
Agile Planning for SoC Design
Agile Planning for SoC Design
Missed milestones, lack of traceability, and costly respins. These are examples of what you risk if you do not take planning seriously during semiconductor design. A rock-solid planning process in the SOC Design process is a must. At the same time, the era of innovation is changing the way teams organize their work. Driven by… Read More »Agile Planning for SoC Design
2 events,
Exploring Andes’ NX27V Vector Processor Instructions
Exploring Andes’ NX27V Vector Processor Instructions
Join Dr. Thang Tran, Principal Architect of Andes Technology Corp. and veteran of high-performance computing (HPC), on September 29, 2021, at 09:00 AM PDT for the last in his four-part masterclass series on demystifying the RISC-V Vector Extension. In this session, Dr. Tran presents examples using vector instructions based on Andes NX27V. He discusses NX27V performance,… Read More »Exploring Andes’ NX27V Vector Processor Instructions
Common Challenges when Designing IoT PCBs – And How to Solve Them with Cadence
Common Challenges when Designing IoT PCBs – And How to Solve Them with Cadence
While IoT devices may seem simple to the end users (which is good), the electrical design complexity of these devices is often very high. Designers are required to work with limited board space while functionality and speed requirements continue to increase. These tight spaces, combined with the required highspeed signaling, leads to increased susceptibility to… Read More »Common Challenges when Designing IoT PCBs – And How to Solve Them with Cadence
3 events,
IP Based Digital Design Management that Goes Beyond the Basics
IP Based Digital Design Management that Goes Beyond the Basics
oin us on Thursday, September 30th to learn why common design management capabilities are not enough and what next generation capabilities are needed for IP based digital design management. Register Today! Here’s what you can learn: Complete digital design management checklist Tagging, branching, and merging Project BOM and IP conflicts Logistics: The webinar will be… Read More »IP Based Digital Design Management that Goes Beyond the Basics
Scalable HPC platform and memory expansion techniques using Die-to-Die and LPDDR subsystems
Scalable HPC platform and memory expansion techniques using Die-to-Die and LPDDR subsystems
With advanced packaging and interface solutions, it is possible to connect multiple CPU clusters (near or far) and share external memory resources among them. We will review some of the IPs required to build such a platform and recommend applications that can benefit from it. This webinar will be useful to designers, architects, and application… Read More »Scalable HPC platform and memory expansion techniques using Die-to-Die and LPDDR subsystems
Avoiding SoC Security Threats – What Verification Engineers Should Know
Avoiding SoC Security Threats – What Verification Engineers Should Know
Thursday, September 30, 2021 | 11:00 -11:30 a.m. PDT The development of secure systems is of paramount importance in this age of software intensive electronic systems. Security weaknesses in the SoC hardware can lead to vulnerabilities that may be exploited later on by malicious software. These challenging problems must be addressed pre-silicon and require rigorous… Read More »Avoiding SoC Security Threats – What Verification Engineers Should Know