Webinar
Formal 101 – Exhaustive Scoreboarding and Data Integrity Verification Made Easy
Verifying the correct passage of data through a DUT in constrained-random simulation is easy to do for basic I/O cases – data loss, obvious corruption, and 1-1 data passage. But… Read More »Formal 101 – Exhaustive Scoreboarding and Data Integrity Verification Made Easy
Agile Planning for SoC Design
Missed milestones, lack of traceability, and costly respins. These are examples of what you risk if you do not take planning seriously during semiconductor design. A rock-solid planning process in… Read More »Agile Planning for SoC Design
Exploring Andes’ NX27V Vector Processor Instructions
Join Dr. Thang Tran, Principal Architect of Andes Technology Corp. and veteran of high-performance computing (HPC), on September 29, 2021, at 09:00 AM PDT for the last in his four-part masterclass… Read More »Exploring Andes’ NX27V Vector Processor Instructions
Common Challenges when Designing IoT PCBs – And How to Solve Them with Cadence
While IoT devices may seem simple to the end users (which is good), the electrical design complexity of these devices is often very high. Designers are required to work with… Read More »Common Challenges when Designing IoT PCBs – And How to Solve Them with Cadence
IP Based Digital Design Management that Goes Beyond the Basics
oin us on Thursday, September 30th to learn why common design management capabilities are not enough and what next generation capabilities are needed for IP based digital design management. Register… Read More »IP Based Digital Design Management that Goes Beyond the Basics
Avoiding SoC Security Threats – What Verification Engineers Should Know
Thursday, September 30, 2021 | 11:00 -11:30 a.m. PDT The development of secure systems is of paramount importance in this age of software intensive electronic systems. Security weaknesses in the… Read More »Avoiding SoC Security Threats – What Verification Engineers Should Know
Scalable HPC platform and memory expansion techniques using Die-to-Die and LPDDR subsystems
With advanced packaging and interface solutions, it is possible to connect multiple CPU clusters (near or far) and share external memory resources among them. We will review some of the… Read More »Scalable HPC platform and memory expansion techniques using Die-to-Die and LPDDR subsystems
DesignCon Digital
This online event from the producers of DesignCon features an education program with on-demand webinars presented by a standout speaker list, suppliers with easy-to-find products and services, and multiple matchmaking… Read More »DesignCon Digital
Keeping Latency to a Minimum with 400G/800G Ethernet IP
A large volume of data is required for high performance computing (HPC) workloads in data centers. As a result, enabling data processing between machines and servers across long reach channels… Read More »Keeping Latency to a Minimum with 400G/800G Ethernet IP
Addressing Growing Security Challenges with JasperGold
Join Cadence® Training and Product Engineering Architect Joerg Mueller and Senior Application Engineer Tom Weiss for this free technical training webinar. As a chip designer, you’re probably spending as much… Read More »Addressing Growing Security Challenges with JasperGold
Benefits of a Common Methodology for Emulation and Prototyping
Many design teams have used some form of hardware verification throughout their verification cycle for years now. Some engineering teams prefer to use emulation, some prefer to use prototyping, and… Read More »Benefits of a Common Methodology for Emulation and Prototyping
UVM for FPGAs (Part 4): IEEE 1800.2 UVM Updates
Abstract: Started with an early adaptor release as Accellera 1.0a, UVM has evolved into few significant versions including UVM 1.1 and UVM 1.2. As with many popular useful standards, UVM… Read More »UVM for FPGAs (Part 4): IEEE 1800.2 UVM Updates