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DFT for chiplets & 3D ICs using Tessent Multi-die
3D IC (2.5D/3D) designs are on the rise. Design for Test (DFT) for chiplets must be general purpose so they can be tested stand alone and easy to test after… Read More »DFT for chiplets & 3D ICs using Tessent Multi-die
Smart methods for DFT chip architecture & validation
Combining market-leading design-for-test (DFT) technologies with best-in-class netlist synthesis allows you to achieve DFT success more quickly. Many customers, including those for emulation and IC test, have challenges with scaling… Read More »Smart methods for DFT chip architecture & validation
AI-Driven 3D System Analysis & Optimization for EM Antenna/RF Problems
Antenna/RF design problems often involve the optimization of many variables, requiring numerous evaluations (EM simulations) using traditional optimization methods. Design engineers need an intelligent, accurate, and easy-to-use simulation platform and… Read More »AI-Driven 3D System Analysis & Optimization for EM Antenna/RF Problems
Cracking the Power Code: Innovative Approach to SoC Power Optimization
Power is the biggest factor impacting semiconductors from custom silicon to CPU/GPU products. System-level Power modeling and simulation is needed to measure power accurately and efficiently. The scope of power… Read More »Cracking the Power Code: Innovative Approach to SoC Power Optimization
Innovative Approach to SoC Power Optimization
Power is the biggest factor impacting semiconductors from custom silicon to CPU/GPU products. System-level Power modeling and simulation is needed to measure power accurately and efficiently. The scope of power… Read More »Innovative Approach to SoC Power Optimization
Innovative Technologies, Tools, and Methodologies for Space Applications
In the world of space applications, reliability is paramount. As the space sector continues to experience rapid growth and evolution, new challenges are emerging to meet the demands of various… Read More »Innovative Technologies, Tools, and Methodologies for Space Applications
AI-Driven EM-IR Design Closure
IR drop closure is becoming a major challenge for designers on advanced nodes. The number of violations at signoff has increased significantly, leading to longer turnaround time (TAT) or violations… Read More »AI-Driven EM-IR Design Closure
The Next Generation of 3DIC Interposer/InFO Design
In recent years, the semiconductor industry has experienced a breakthrough in the onset of 2.5D and 3D chiplet-based products. These products promise to extend the limits of Moore’s Law while… Read More »The Next Generation of 3DIC Interposer/InFO Design
Accelerating AI Applications Using Custom RISC-V based SIMD/VLIW DSPs
The revolution in AI triggers an increased awareness for application-specific instruction-set processors (ASIPs). These processors implement a specialized instruction-set architecture (ISA) tailored to the AI application domain, often starting from… Read More »Accelerating AI Applications Using Custom RISC-V based SIMD/VLIW DSPs
Questa RDC Assist – Improving designer productivity and enabling faster RDC verification closure with machine learning
In 2021 Siemens EDA released CDC Assist. CDC Assist is an ML powered feature that empowers users to configure, debug, and close CDC on designs more rapidly. Following the success… Read More »Questa RDC Assist – Improving designer productivity and enabling faster RDC verification closure with machine learning
Addressing the Challenges of PCB Design for Manufacturing
Manufacturing issues can be a big reason why your project timelines get derailed and even result in costly failures. By understanding common errors that occur while designing or creating your… Read More »Addressing the Challenges of PCB Design for Manufacturing
Debugging Features of UVM
A UVM testbench is a large and complex piece of software. Like any other large and complex piece of software, a verification environment written using UVM will require debugging at… Read More »Debugging Features of UVM