Webinar
Learn How to Perform Device Meshing with Silvaco’s Victory Mesh TCAD Solution
ictory Mesh is Silvaco’s TCAD solution for device meshing and solid modeling. Victory Mesh creates suitable meshes from process structures for device simulation. For example, the results produced by process… Read More »Learn How to Perform Device Meshing with Silvaco’s Victory Mesh TCAD Solution
Boost Your CXL Verification from IP to System Level
Register now for this CadenceTECHTALK, where we will walk you through CXL verification challenges from IP level to system level and demonstrate how these challenges can be significantly mitigated using… Read More »Boost Your CXL Verification from IP to System Level
Future of Semiconductor Design: 2022 Predictions & Trends
As the semiconductor industry continues to grow at an exponential rate, so has its challenges. We recently surveyed semiconductor design professionals on the biggest challenges, trends, and opportunities facing the… Read More »Future of Semiconductor Design: 2022 Predictions & Trends
Everything You Need to Know about SystemVerilog Arrays
This webinar gives a comprehensive guide to all aspects of SystemVerilog arrays: ordinary static arrays, dynamic arrays, queues and associative arrays. It also includes array methods and practical examples. Topics:… Read More »Everything You Need to Know about SystemVerilog Arrays
Exploring a Software First Approach to Avoid SoC Re-spins
Traditional coverage-based verification methods are no longer sufficient to verify complex SoCs integrating many processor cores and IP subsystems. To conquer the verification challenge of complex SoCs, companies are shifting… Read More »Exploring a Software First Approach to Avoid SoC Re-spins
Managing the Complexity of FinFET Standard Cell Layout with Cello
FinFET technologies have enabled designs with increased density and performance while reducing power, when compared to MOSFET. However, this comes at a cost of increased design complexity. Not only are… Read More »Managing the Complexity of FinFET Standard Cell Layout with Cello
3DIC Design from Concept to Silicon
For some high-performance computing (HPC) designs, monolithic SoCs aren’t producing the scalability and yield that designers are looking for. New trends towards 3DIC design are emerging introducing new design challenges,… Read More »3DIC Design from Concept to Silicon
Verification of PCIe-based FPGA Designs Requiring DO-254 Compliance (US)
PCIe-based FPGA designs are becoming popular within avionics systems. However, the verification of such designs for DO-254 compliance with design assurance level (DAL) A or B is problematic. FPGA designs… Read More »Verification of PCIe-based FPGA Designs Requiring DO-254 Compliance (US)
ACCELERATE PACKAGE THERMAL MODELING IN ELECTRONICS COOLING DESIGN WEBINAR
How do you generate faster, accurate semiconductor package thermal models? This webinar focuses on thermal modeling of electronics packages to predict component temperature in system-level electronics cooling simulations during development.… Read More »ACCELERATE PACKAGE THERMAL MODELING IN ELECTRONICS COOLING DESIGN WEBINAR
Optimized Chip Design with Main Processors and AI Accelerators
Presented by Paul Karazuba, VP of Marketing, Expedera & John Min, Director of Field Application Engineering, Andes Technology About this talk As AI capability is beginning large-scale deployment into edge… Read More »Optimized Chip Design with Main Processors and AI Accelerators
Balancing analog layout parasitics in MOSFET differential pairs
The MOSFET differential pair is a key part of many analog circuits e.g. opamps, comparators, LDOs, etc. A differential pair applies gain to the difference between two signals and has… Read More »Balancing analog layout parasitics in MOSFET differential pairs
How to Improve Physical Verification Productivity with SmartDRC/LVS
Physical Verification is the most critical stage of IC design. SmartDRC/LVS is a new physical verification tool for analog, digital and mixed-signal ICs including design rule checks (DRC), layout connectivity… Read More »How to Improve Physical Verification Productivity with SmartDRC/LVS