Webinar
Calendar of Events
S Sun
M Mon
T Tue
W Wed
T Thu
F Fri
S Sat
1 event,
Intelligent Cross-Platform Workflows for RF PCB Integration
Intelligent Cross-Platform Workflows for RF PCB Integration
The last webinar in The Cadence® AWR® V16 for RF Design Excellence Webinar Seriesintroduces groundbreaking cross-platform workflows from AWR® software to Allegro® PCB Designer, which help to deliver up to a 50% reduction in turnaround time compared to competing solutions. RF IP integration within a larger mixed-signal PCB system is hampered by disjointed workflows between… Read More »Intelligent Cross-Platform Workflows for RF PCB Integration
1 event,
Understanding Random Stability in SystemVerilog and UVM
Understanding Random Stability in SystemVerilog and UVM
Webinar Overview: A common issue with constrained random simulation is being able to reproduce random stimulus for debug purposes and for locking down regressions test suites. This is especially problematic when the source code needs to be modified and is known in SystemVerilog as random stability. In this webinar, we explain: Random stability in SystemVerilog… Read More »Understanding Random Stability in SystemVerilog and UVM
1 event,
Constraint Random Verification with Python and Cocotb
Constraint Random Verification with Python and Cocotb
Abstract: Testing digital hardware has never been an easy job, and it won’t get easier any time soon. But that doesn’t mean writing test code can’t be enjoyable and productive! Cocotb, an approach to use Python as verification language, is bringing the joy back to verification. It allows developers to start with small, directed testbenches,… Read More »Constraint Random Verification with Python and Cocotb
3 events,
Boost LPDDR5 Verification from IP to System Level
Boost LPDDR5 Verification from IP to System Level
Overview Low power DRAM is being adopted in a wide array of markets, including automotive, PCs and networking systems built for 5G and AI applications. The specification complexity is increasing to meet higher bandwidth, better performance and extended latencies for multiple use cases. Ensuring that JEDEC low-power double data rate 5 (LPDDR5) specification and overall… Read More »Boost LPDDR5 Verification from IP to System Level
CXL and IDE: Important Considerations of Protecting High Speed Interconnects
CXL and IDE: Important Considerations of Protecting High Speed Interconnects
In a few short years, CXL (Compute Express Link) has evolved from an idea to a rapidly proliferating low latency interconnect standard being adopted into data centers, high performance computing, and cloud computing. However, as the adoption has increased, so has the security threat model users face. To address this, the CXL 2.0 standard has… Read More »CXL and IDE: Important Considerations of Protecting High Speed Interconnects
Workforce Shortages—Meeting Challenges for the Semiconductor Industry
Workforce Shortages—Meeting Challenges for the Semiconductor Industry
As demand for semiconductors is increasing, foundries and other makers of chips are expanding their manufacturing capacities. With new fabs bringing thousands of new jobs to the US, Texas is ready to secure many of those positions. Where will we find the talent to fill the upcoming surge of engineering and technical personnel needed to support our… Read More »Workforce Shortages—Meeting Challenges for the Semiconductor Industry
3 events,
Virtual Prototyping Day – Silver: Accelerate Your Innovation with Virtual ECUs
Virtual Prototyping Day – Silver: Accelerate Your Innovation with Virtual ECUs
Synopsys invites you to the Virtual Prototyping Day – Silver, a virtual event on virtual ECUs and applications in automotive software development. Users share their experiences with the latest techniques and methodologies using Synopsys Silver virtual ECUs. Attendees will learn about how Silver supports new trends and industry standards in automotive with presentations by Daimler,… Read More »Virtual Prototyping Day – Silver: Accelerate Your Innovation with Virtual ECUs
Enabling Effective Design & Layout Collaboration for Next Generation Analog and Mixed-Signal Designs
Enabling Effective Design & Layout Collaboration for Next Generation Analog and Mixed-Signal Designs
Analog designers appreciate the importance of tight communication between layout and design teams, yet with geographically dispersed teams this can be a big challenge. Close collaboration between circuit designer and layout designer is essential for creating high-quality analog layouts. With this close connection and sharing feedback in a consistent way, analog designers can be sure… Read More »Enabling Effective Design & Layout Collaboration for Next Generation Analog and Mixed-Signal Designs
The Evolution of Process TCAD in Semiconductor R&D and Manufacturing
The Evolution of Process TCAD in Semiconductor R&D and Manufacturing
Shela Aboud, Ph.D., Synopsys Today, nearly every aspect of an integrated circuit is designed using EDA software. Technology computer aided design (TCAD) tools are used for modeling front-end-of-line manufacturing, including the fabrication and electrical characterization of individual transistors. I will discuss how TCAD has evolved to keep up with technology evolution and how new drivers… Read More »The Evolution of Process TCAD in Semiconductor R&D and Manufacturing
1 event,
What’s Needed to Perform End-to-End Testing for 5G Open Radio Access Network SoCs
What’s Needed to Perform End-to-End Testing for 5G Open Radio Access Network SoCs
Testing an O-RAN Radio Unit (O-RU) SoC at full scale implies sending realistic traffic, in conformance with current specifications and at the right time on the right interfaces to simulate complex scenarios and cover as many corner cases as possible. It requires a robust debug methodology which can provide quick turn around and appropriate window… Read More »What’s Needed to Perform End-to-End Testing for 5G Open Radio Access Network SoCs
2 events,
Practical Flows for Continuous Integration: Making The Most of Your EDA Tools
Practical Flows for Continuous Integration: Making The Most of Your EDA Tools
Verifying changes to RTL and testbench code prior to releasing to the rest of your team is the best way to avoid committing bugs that cause massive, team-wide disruptions. This webinar takes you through example tool flows that, when used within a Continuous Integration (CI) system, can avoid or even eliminate those bugs and disruptions.… Read More »Practical Flows for Continuous Integration: Making The Most of Your EDA Tools
Accelerating Analog Layout
Accelerating Analog Layout
The growing demand for analog features on IoT devices means that analog designers are under constant pressure to complete more designs faster than ever. For most layout designers, analog layout remains a largely manual task, which creates real challenges for today’s pressured designers. Pulsic presents a new solution for analog layout automation. Animate Preview accelerates… Read More »Accelerating Analog Layout
2 events,
CadenceTECHTALK: Power and Energy Optimization Using Tensilica IP
CadenceTECHTALK: Power and Energy Optimization Using Tensilica IP
Join us as Cadence experts describe common challenges and solutions in creating an efficient and accelerated flow that will meet technical requirements for accurately measuring the power, energy, and system performance while making essential design tradeoffs to meet your aggressive time-to-market schedule. In this CadenceTECHTALK, you will learn how to: Address the challenges of accelerating… Read More »CadenceTECHTALK: Power and Energy Optimization Using Tensilica IP
A Scalable Approach to 2X Faster Turnaround Time for Arm Neoverse N2 Core Design Verification
A Scalable Approach to 2X Faster Turnaround Time for Arm Neoverse N2 Core Design Verification
In the latest generation of multiple processor SoCs, designers are adding cache-coherent agents beyond the multi-processor clusters, making it a complex verification challenge. System coherency needs to be maintained at various levels, beginning at the cluster level, and continuing, across the cache coherent interconnect and across chips through chip-to-chip gateways. The coherency protocol across interconnects… Read More »A Scalable Approach to 2X Faster Turnaround Time for Arm Neoverse N2 Core Design Verification
1 event,
Accelerate Semiconductor Technology Development and Innovation
Accelerate Semiconductor Technology Development and Innovation
Seminar Overview Join our online TCAD Seminar to learn about the application of Synopsys TCAD solutions to accelerate the research, development and optimization of semiconductor technologies. The seminar tracks cover all major semiconductor technologies, from advanced logic and memory to analog, power and optoelectronics. The solutions presented in this seminar are based on the industry-standard… Read More »Accelerate Semiconductor Technology Development and Innovation
1 event,
Everything you wanted to know about VHDL configurations
Everything you wanted to know about VHDL configurations
VHDL configurations are a much maligned, much ignored part of the VHDL language. Consequently, many VHDL designers find them quite scary. This webinar seeks to answer the questions you may not have had answered in the past; shedding light on the mystery of VHDL configurations and showing a practical example of how to apply them,… Read More »Everything you wanted to know about VHDL configurations
1 event,
LIVE WEBINAR: How to Simplify the Verification of Bus Interfaces (US)
LIVE WEBINAR: How to Simplify the Verification of Bus Interfaces (US)
Abstract: Today’s FPGAs and SoC FPGAs use various types of bus interconnect - such as AXI, APB, AHB, Avalon or Wishbone - for both internal (IP-level) and external communication. A recently added feature to Aldec’s ALINT-PRO allows designers to extract, review and verify the correctness of bus interface connections. In addition, ALINT-PRO is capable of… Read More »LIVE WEBINAR: How to Simplify the Verification of Bus Interfaces (US)