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IESA Vision Summit 2022
The LaLIT Bangalore, IndiaThe 17th edition of IESA flagship event, IESA Vision Summit 2022 is scheduled on 12th and 13th October 2022 in Bengaluru. This is our flagship event where most of the Semiconductor and ESDM companies from India and the world come under one roof. The objective of the event is to enable DESIGN IN INDIA and… IESA Vision Summit 2022
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Everything You Need to Know About Virtual ECU Abstraction Levels
Growing electronic/electrical (E/E) architecture complexity and software content in modern vehicles has propelled the use of virtualization-based testing to develop and validate functions and software components more effectively. The simulation of electronic control units (ECUs) as virtual ECUs (vECUs) has found rapid adoption in several phases of automotive development. This 30-minute Webinar will provide a… Everything You Need to Know About Virtual ECU Abstraction Levels
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Assertions-Based Verification for VHDL Designs
Assertion-based verification (ABV) enables the use of assertions for the efficient verification of low-level design properties. These assertions could be verified by simulation and formal verification methods. The VHDL 2008 standard includes Property Specification language (PSL) to express design properties for both simulation and static formal analysis. For mixed-mode simulations of VHDL designs with SystemVerilog… Assertions-Based Verification for VHDL Designs
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SNUG Europe
Hilton Munich Airport Terminalstraße Mitte 20, 85356 München-Flughafen, Munich, GermanySince 1991, the Synopsys Users Group (SNUG) has represented a global design community focused on innovating from Silicon to Software. Today, as the electronics industry’s largest user conference, SNUG brings together over 12,000 Synopsys tool and technology users around the world. In addition to peer-reviewed technical presentations and insightful keynotes from industry leaders, SNUG provides… SNUG Europe
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Cadence Further Streamlines MMIC, RFIC, and RF SiP Design Workflows
Demand for next-generation wireless communication, aerospace, and transportation systems is driving the need for high-performance, cost-sensitive silicon RFICs and III-V compound semiconductor monolithic microwave integrated circuits (MMICs), often integrated into advanced system-in-package (SiP) modules. Join us as we demonstrate how the key new features of the Cadence® AWR Design Environment platform: Accelerates design entry and platform design sharing to… Cadence Further Streamlines MMIC, RFIC, and RF SiP Design Workflows
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Improving Efficiency and Quality of Verification Environments with Automation
Bugs can be introduced at any stage in the hardware design development process and escape into tapeout if the verification environment is unqualified. Measuring and improving verification effectiveness to prevent bugs during functional verification is the key to taping out bug-free high-quality designs. Verification environments are often more complex than the designs they help verify.… Improving Efficiency and Quality of Verification Environments with Automation
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RISC-V Con
DoubleTree Hotel 2050 Gateway Place, San Jose, CA, United StatesIn order to foster stronger collaboration on RISC-V across the computing industry, RISC-V CON focuses on this disruptive technology, demonstrating its benefits and identifying commercial strategies. Through RISC-V CON, the RISC-V community and ecosystem can share the most up-to-date development and RISC-V based products and solutions. Seventeen years in business and a Founding Premier member… RISC-V Con
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Synopsys Photonic Symposium
Photonics and photonic IC technologies are crucial to support rapidly evolving internet, healthcare, mobility, and security needs. Driven by data communications, photonic ICs are moving rapidly from the laboratory to mainstream and fueling a wave of innovations and product introductions. Join our virtual Photonic Symposium to hear about the latest developments, application requirements, best practices,… Synopsys Photonic Symposium
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Jasper User Group 2022
Cadence San Jose, CA, United StatesReady to share and discuss the latest design and verification best practices with your peers from around the world? It’s time for our annual Jasper™ User Group Conference held on October 19 and 20 at the Cadence San Jose campus. This interactive, in-depth technical conference connects designers, verification engineers, and engineering managers from around the… Jasper User Group 2022
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Best Practices to Achieve the Highest Performance using Xcelium Logic Simulator
Simulator performance is critical owing to the exponentially increasing complexity of SoC designs and shrinking market time. Cadence® Xcelium™ is a leader in simulation performance, and we focus relentlessly on improving the core performance of the simulator. We keep developing new performance optimizations that are delivered with each new release of Xcelium. It is easy to achieve… Best Practices to Achieve the Highest Performance using Xcelium Logic Simulator
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Optimizing Simulations for Efficient Coverage Collection
Coverage is an essential part of any verification environment. Coverage can be simple as a statement and branch coverage, or it can be more complex as a covergroup with constrained-random tests. Implementation, collection and analysis of coverage on your designs might look challenging but with a few steps you can optimize your design flow to… Optimizing Simulations for Efficient Coverage Collection
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The Dawn of AI Revolution in Chip Design
Abstract: We are at the dawn of an AI revolution for every human activity including chip design. The AI revolution in chip design is absolutely necessary because of key macro trends influencing chip design and would further accelerate the AI revolution in all other fields. In this talk I will start with my personal journey… The Dawn of AI Revolution in Chip Design
12 events found.