41st IEEE VLSI Test Symposium 2023
Hyatt Regency Mission Bay Spa & Marina 1441 Quivira Road, San Diego, CA, United StatesThe IEEE VLSI Test Symposium (VTS) explores emerging trends and novel concepts in test, validation, yield, reliability, and security of microelectronic circuits and systems. The symposium will take place on April 24-26, 2023, at the Hyatt Regency Mission Bay Spa & Marina, 1441 Quivira Road, San Diego, CA, USA. The program includes keynotes, scientific paper… Read More »41st IEEE VLSI Test Symposium 2023
RSAConference 2023
Moscone Center 747 Howard Street, San Francisco, CA, United StatesWhere the World Talks Security™ Don’t miss the opportunity to take your knowledge and skills to the next level at RSAC 2023. Not sure if the complete Conference experience will work with your schedule and budget? We offer several pass options—including an On Demand Pass. But hurry, our final discount ends Friday, April 21! In… Read More »RSAConference 2023
The ROI of User Experience Design: Increase Sales and Minimize Costs
In today's competitive landscape for IoT, edge, and cloud solutions, User Experience (UX) design has become more crucial than ever in achieving customer and business goals. During this live webinar, we will explore how UX design affects everything from sales, customer retention, time-to-market, to internal support and development costs. We'll delve into key principles of… Read More »The ROI of User Experience Design: Increase Sales and Minimize Costs
DVClub Europe – Performance Testing and Analysis
Discuss the performance verification challenges posed by complex SoC with distributed cache from cluster, to interconnect to die-to-die. Agenda (BST) 12:00 Welcome and Introduction – Mike Bartley, Tessolve 12:00 Nick Heaton, Cadence Design Systems - SoC Verification in a Multi-chip, Multi-die world 12:30 TBD 13:00 TBD 13:30 Close Additional Information For additional information please visit… Read More »DVClub Europe – Performance Testing and Analysis
IP SoC Silicon Valley 23
Computer History Museum 1401 N. Shoreline Blvd, Mountain View, CA, United StatesD&R IP-SoC Silicon Valley 2023 Day is the unique worldwide Spring event fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems. IP-SoC providers, the seed of innovation in Electronic Industry, are invited to highlight their latest products and services and share their vision about the next innovation steps in the Electronic Industry.… Read More »IP SoC Silicon Valley 23
TSMC – North America Technology Symposium
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesJoin us and learn about: TSMC's smartphone, HPC, IoT, and automotive platform solutions TSMC's advanced technology progress on 5nm, 4nm, 3nm, 2nm processes and beyond TSMC's specialty technology breakthroughs on ultra-low power, RF, embedded memory, power management, sensor technologies, and more TSMC 3DFabric™ advanced packaging technology advancement on InFO, CoWoS®, and SoIC TSMC's manufacturing excellence,… Read More »TSMC – North America Technology Symposium
Advancing Magnetic Memory Technology with Atomistic Modeling
In this event, experts from Martin-Luther-Universitat Halle Wittenberg, University of York, and Synopsys QuantumATK will present how to use ab initio DFT modeling and atomistic spin dynamics simulations of MTJs to guide and accelerate the technological development of magnetic memory such as STT and SOT-MRAM. Investigating the potential of novel magnetic tunnel junction (MTJ) materials… Read More »Advancing Magnetic Memory Technology with Atomistic Modeling
Maximize Performance and Efficiency of Multi-die Data Center Chip Designs with Arm CoreLink CMN-700 and Synopsys Platform Architect
This webinar will showcase the design, analysis, and optimization of a multi-die fabric architecture based on the next generation Arm® CoreLink™ CMN-700 interconnect, a high-performance cache coherent interconnect solution designed for complex multi-die system-on-chip (SoC), such as those found in data centers. Attendees will learn how to use the Arm CMN-700 Performance Model in Synopsys… Read More »Maximize Performance and Efficiency of Multi-die Data Center Chip Designs with Arm CoreLink CMN-700 and Synopsys Platform Architect
How Deep Data Analytics Accelerates SoC Time-To-Market by 6 Months
This webinar will cover how using deep data analytics: Accelerates time-to-market by 20-25% (equivalent to six months in this example), ensuring the product is first to market and able to capitalize on this advantage. Reduces design and development costs by nearly $25M, amounting to a 9% cost savings. Leads to a higher quality product by improving performance by… Read More »How Deep Data Analytics Accelerates SoC Time-To-Market by 6 Months
CadenceTECHTALK: System-Level Thermal Signoff from Chips Through to Racks
Today’s modern electronic designs require ever more functionality and performance to meet consumer demand. These challenges become more critical and complex when resistive losses in PCB and package structures are significant since resistive losses are temperature dependent. In this webinar, we will look at an electrothermal co-simulation solution for the full hierarchy of electronic systems… Read More »CadenceTECHTALK: System-Level Thermal Signoff from Chips Through to Racks
The Path to 1.6TbE with 224G Ethernet PHY IP
The need for faster and more efficient Ethernet solutions has never been greater, as the demands of high-performance computing and the rise of big data continue to grow. Join us as we explore the main challenges faced in scaling Ethernet to 1.6T and how the high-performance computing is changing the Ethernet landscape. In this webinar,… Read More »The Path to 1.6TbE with 224G Ethernet PHY IP
The Power of VHDL’s VHPI
The programming interfaces of logic simulators are largely the domain of specialists writing proprietary tools and extensions and are only vaguely in the consciousness of many design and verification engineers, if aware at all. Yet the simplest use of such interfaces opens up a whole world of possibilities in extending what is achievable in verifying… Read More »The Power of VHDL’s VHPI