ISCAS 2023
Monterey, CA Monterey, CA, United StatesThe IEEE International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society and the world’s premiere forum for researchers in the… Read More »ISCAS 2023
Embedded Vision Summit 2023
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesThe Summit attracts a global audience of technology professionals from companies developing computer vision and edge AI-enabled products including embedded systems, cloud solutions and mobile applications. Why attend? It's a… Read More »Embedded Vision Summit 2023
Extending RISC Processors into Flexible Accelerators using ASIP Designer
Case Studies in Low-Power Smart Vision and Post-Quantum Cryptography Applications The slow-down of Moore’s law and Dennard scaling triggered an increased awareness for application-specific instruction-set processors (ASIPs). These processors implement… Read More »Extending RISC Processors into Flexible Accelerators using ASIP Designer
DENSO discusses Verification of network relay performance using VisualSim
Want to learn how Tier One suppliers are using network modeling and simulation in the design and optimization of network topology and gateway architecture. Then attend this Webinar by DENSO.… Read More »DENSO discusses Verification of network relay performance using VisualSim
Advancing MRAM Technology with Atomistic Spin Dynamics Simulations
In this event, experts from Martin-Luther-Universitat Halle Wittenberg, University of York, and Synopsys QuantumATK will present how to use ab initio DFT modeling and atomistic spin dynamics simulations of MTJs… Read More »Advancing MRAM Technology with Atomistic Spin Dynamics Simulations
Requirements for Multi-Die System Success
Wednesday, May 24, 2023 and Thursday, May 25, 2023 The industry is moving to multi-die systems to benefit from the greater compute performance, increased functionality, and new levels of flexibility.… Read More »Requirements for Multi-Die System Success
Accelerate Coverage Closure and Debug with Synopsys AI-Driven Verification Solutions
Synopsys Webinar | Wednesday, May 24, 2023 | 10:00 - 10:45 a.m. IST Engineering resources are getting stretched thinner and thinner as design complexity increases. Automation is a significant driver… Read More »Accelerate Coverage Closure and Debug with Synopsys AI-Driven Verification Solutions
Don’t Take the Risk, Formally Verify Your RISC-V Cores
Synopsys Webinar | Thursday, May 25, 2023 | 9:00 a.m. PT According to a recent Semico Research report, the RISC-V Core IP market is expected to grow at a 34.9%… Read More »Don’t Take the Risk, Formally Verify Your RISC-V Cores
SiFive Maximizes Compute Density With Its RISC-V Processor Cores
IP vendor SiFive has been at the forefront of RISC-V’s rapidly growing adoption across a wide array of markets and applications. In this joint presentation with Ansys, SiFive will describe… Read More »SiFive Maximizes Compute Density With Its RISC-V Processor Cores
STAC Summit
New York Marriott Marquis 1535 Broadway, New York City, NY, United StatesSTAC Summits bring together CTOs and other industry leaders responsible for solution architecture, infrastructure engineering, application development, machine learning/deep learning engineering, data engineering, and operational intelligence to discuss important technical… Read More »STAC Summit
Advanced Testbench for a Simple DUT
Abstract: Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series, we will present a step-by-step approach… Read More »Advanced Testbench for a Simple DUT
Accelerate Software Innovation Through Target-Optimized Code Generation and Virtual Prototypes
Increasingly complex automotive systems are driving the need for new and powerful E/E architectures, and new technology is emerging that offers a significant computational increase compared to previous generation SoCs.… Read More »Accelerate Software Innovation Through Target-Optimized Code Generation and Virtual Prototypes