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Cadence Further Streamlines MMIC, RFIC, and RF SiP Design Workflows
Demand for next-generation wireless communication, aerospace, and transportation systems is driving the need for high-performance, cost-sensitive silicon RFICs and III-V compound semiconductor monolithic microwave integrated circuits (MMICs), often integrated into advanced system-in-package (SiP) modules.… Cadence Further Streamlines MMIC, RFIC, and RF SiP Design Workflows
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Improving Efficiency and Quality of Verification Environments with Automation
Bugs can be introduced at any stage in the hardware design development process and escape into tapeout if the verification environment is unqualified. Measuring and improving verification effectiveness to prevent… Improving Efficiency and Quality of Verification Environments with Automation
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RISC-V Con
DoubleTree Hotel 2050 Gateway Place, San Jose, CA, United StatesIn order to foster stronger collaboration on RISC-V across the computing industry, RISC-V CON focuses on this disruptive technology, demonstrating its benefits and identifying commercial strategies. Through RISC-V CON, the… RISC-V Con
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Synopsys Photonic Symposium
Photonics and photonic IC technologies are crucial to support rapidly evolving internet, healthcare, mobility, and security needs. Driven by data communications, photonic ICs are moving rapidly from the laboratory to… Synopsys Photonic Symposium
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Jasper User Group 2022
Cadence San Jose, CA, United StatesReady to share and discuss the latest design and verification best practices with your peers from around the world? It’s time for our annual Jasper™ User Group Conference held on… Jasper User Group 2022
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Best Practices to Achieve the Highest Performance using Xcelium Logic Simulator
Simulator performance is critical owing to the exponentially increasing complexity of SoC designs and shrinking market time. Cadence® Xcelium™ is a leader in simulation performance, and we focus relentlessly on improving the… Best Practices to Achieve the Highest Performance using Xcelium Logic Simulator
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Optimizing Simulations for Efficient Coverage Collection
Coverage is an essential part of any verification environment. Coverage can be simple as a statement and branch coverage, or it can be more complex as a covergroup with constrained-random… Optimizing Simulations for Efficient Coverage Collection
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The Dawn of AI Revolution in Chip Design
Abstract: We are at the dawn of an AI revolution for every human activity including chip design. The AI revolution in chip design is absolutely necessary because of key macro… The Dawn of AI Revolution in Chip Design
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The Applied Superconductivity Conference
Hawaii Convention Center 1801 Kalākaua Ave, Honolulu, HI, United StatesThe Applied Superconductivity Conference is the premier international conference on applied superconductivity and quantum computing. Engineers, scientists and industry representatives interested in developments related to the electronics and materials for… The Applied Superconductivity Conference
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Arm DevSummit
Palace of Fine Arts 3601 Lyon Street, San Francisco, CA, United StatesAfter two years of virtual networking, we’re thrilled to announce the return of Arm DevSummit in-person in October. As you’re a past attendee, we’re delighted to welcome you to this… Arm DevSummit
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TSMC 2022 OIP – California
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesJoin the TSMC 2022 Open Innovation Platform Ecosystem Forum and learn from OIP partners how to leverage their technology for your design challenges! Register Now Learn About: Emerging advanced node… TSMC 2022 OIP – California
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Protium Enterprise Prototyping: Higher Productivity, Lower Costs
Prototyping has become essential for chip and IP developers as they deal with exponentially greater testing requirements that come with growing design size, software content, and input data and workloads… Protium Enterprise Prototyping: Higher Productivity, Lower Costs
12 events found.