Calendar of Events
|
Sunday
|
Monday
|
Tuesday
|
Wednesday
|
Thursday
|
Friday
|
Saturday
|
|---|---|---|---|---|---|---|
|
1 event,
Attend and hear research, challenges, and breakthroughs as you gather with colleagues in San Jose Join other leading researchers who are solving challenges in optical and EUV lithography, patterning technologies, metrology, and process integration for semiconductor manufacturing and adjacent applications. Five days of exciting content and connecting with your community Plenary talks Technical presentations Networking… SPIE Advanced Lithography + Patterning |
3 events,
Where technology, community and commerce converge MWC Barcelona is the largest and most influential event for the connectivity ecosystem. Whether you’re a global mobile operator, device manufacturer, technology provider, vendor, content owner, or are simply interested in the future of tech, you need to be here. Why? Because it’s the one time of year where… MWC 2024
-
Please join us for our in-person Synopsys Technical Forum, taking place during SPIE Advanced Lithography + Patterning 2024. Attendees will learn about the latest industry trends along with Synopsys Manufacturing's mask synthesis, mask data prep, and lithography simulation solutions. The Tech Forum is peer-to-peer, giving you the opportunity to hear how your lithography colleagues have… Synopsys Technical Forum 2024 |
3 events,
-
Join us in this insightful webinar as we delve into the world of aerospace and defense electrical fault code troubleshooting, unveiling the power of Capital™ Service Explorer. Discover innovative strategies to diagnose issues swiftly, minimizing downtime and optimizing product performance. Explore real-world examples showcasing how Capital Service Explorer facilitates the identification of commonalities among multiple… From code to solution: tools and tactics for aerospace fault code troubleshooting |
3 events,
-
Shift Left with the Modern Design Center Artificial intelligence (AI) is redefining high-speed digital designs. Your ability to design, simulate, and test — using an automated, integrated workflow — is what will set you apart. Whether you are a design team leader, digital designer, or system engineer, this one-day event is for you. We have… Keysight EDA Connect World Tour: Santa Clara – High Speed Digital |
4 events,
-
Shift Left with the Modern Design Center Artificial intelligence (AI) is redefining communication and connectivity. Your ability to design, simulate, and test — using an automated, integrated workflow — is what will set you apart. Whether you are a design team leader, RF designer, or system engineer, this one-day event is for you. We have… Keysight EDA Connect World Tour: Santa Clara – RF Day
-
We often think of Design for Manufacturing (DFM) as the sole responsibility of the fabricator. Over the years, many OEMs have implemented DFM as a final check in their release process, but that approach does not prevent issues within a design from piling up and being left for a DFM engineer to identify and communicate… Manufacturing driven design – DFM within an Xpedition Flow |
0 events,
|
0 events,
|
|
0 events,
|
1 event,
The Design & Verification Conference & Exhibition is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits. The focus of this highly technical conference is on the practical aspects of these technologies and their use in leading-edge projects to encourage attendees… DVCon USA 2024 |
1 event,
|
2 events,
-
Learn how innovative analog IP can help analog design engineers. Agile Analog is transforming the analog IP industry, with Composa, our configurable, multi-process technology that automatically generates analog IP. We offer a wide-variety of novel analog IP solutions for Data Conversion, Power Management, IC Monitoring, Security and Always-On IPs. Applications include High Performance Computing (HPC),… Agile Analog Technology Showcase Event |
3 events,
-
The surge in applications such as AI, HPC, and GPU-intensive workloads requires unparalleled performance, placing cloud vendors and enterprise datacenters under immense pressure to simultaneously maximize power efficiency, reduce costs, and adhere to stringent environmental standards. Join us for a 1-hour panel discussion featuring unique perspectives from industry experts at Intel, Microsoft, Arm and proteanTecs. We will explore… Navigating the Power Challenges of Datacenter Infrastructure
-
As 112G+ data transfer becomes the new normal, companies risk schedule delays unless they improve the efficiency of their multi-board design methodology. An efficient design methodology looks at signal and power integrity early and often as the design progresses. In addition, with the precision required to meet 112G compliance, companies can take extra steps to… Efficient Design Methodology for 112G Interface Compliance |
0 events,
|
0 events,
|
|
0 events,
|
0 events,
|
1 event,
-
Accelerate Layout Creation with Automated Place and Route in Virtuoso Studio How can you cut down custom layout implementation from days to minutes? Custom device-level automated place and route (APR) for advanced nodes has very different requirements than mature node chip assembly routing. With our new unified APR flow-based user interface integrating the various automation… What’s New About Virtuoso Layout Suite? |
1 event,
Inaugural GSA event in partnership with the UK Government. Meet senior business leaders, investors, and public policy officials from around the world. Across two days, join us for exciting discussions on semiconductor innovation for a NetZero economy, with a view on the dramatically changing supply chain, government interventions and industry outlook. Semiconductor Innovation for… GSA International Semiconductor Conference |
2 events,
-
Designers increasingly use complex reset signaling architectures to meet high-performance, low-latency, and low-power requirements. Specifically, independent reset domains are created by complex reset sequences, reset circuitry, and the intermixing of IPs with different reset schemas, power-management domains, and security domains or functionality. This increase in reset signaling complexity is creating new RDC verification challenges that… New Advanced Techniques for Reset Domain Crossing (RDC) Analysis |
0 events,
|
0 events,
|
|
0 events,
|
1 event,
GOMACTech was established primarily to review developments in microcircuit applications for government systems. Established in 1968, the conference has focused on advances in systems being developed by the Department of Defense and other government agencies and has been used to announce major government microelectronics initiatives such as VHSIC and MIMIC, and provides a forum for… GOMACTech 2024 |
3 events,
-
Virtuoso Layout Suite has pioneered in-design DRC checking and fixing in the layout editor. However, many of you have realized that the lack of completeness of rules in the techfile has caused many violations to fall through the cracks and are discovered later during signoff. An in-design DRC checking with signoff rule decks often comes… Virtuoso – Save on Signoff Effort with In-Design DRC and Fill
-
This DVClub focuses on the latest verification techniques in VHDL including UVVM and OSVVM Agenda (GMT) 13:00 Welcome and Introduction – Mike Bartley, Tessolve 13:00 Epsen Tallaksen, EmLogic - Get the right FPGA quality through efficient Specification Coverage (aka Requirement Coverage) 13:30 Jim Lewis, SynthWorks - OSVVM in a NutShell, VHDL’s #1 Verification Methodology 14:00 Close Additional… DVClub Europe: Latest VHDL Verification Techniques |
2 events,
Connecting the Synopsys User Community SNUG conferences have connected Synopsys global users for more than three decades. SNUG 2024 will once again provide a place where users and technical experts can meet, network, and share ideas about chip and system design. Technical Committee SNUG thanks the members of the Technical Committee who volunteer their time… SNUG Silicon Valley 2024 |
5 events,
-
Accelerate Your Designs with Generative AI-Powered Multiphysics Analysis and Optimization How are you addressing the ever-increasing complexity and density of your high-performance electronic systems? What role do electromagnetic effects such as electromagnetic interference (EMI), electromagnetic compatibility (EMC), power integrity, and signal integrity play? Discover how Cadence is transforming electromagnetic (EM) simulation for optimal design performance with… AI-Powered Electromagnetics Symposium
-
With the growing complexities of 3D-ICs, chiplets, advanced packaging, and high-performance boards, engineers need a unified solution that provides early insight and analysis to detect and correct design problems before it is too late. This solution must also offer the ability to simulate the entire design efficiently, providing confidence in system signoff. Join our webinar… Shift-Left Thermal Analysis with AI-Enabled Celsius Studio Platform
-
Based on recent industry research, the FPGA market was valued at approximately USD 7.5 Billion in 2023, with an expected compound annual growth rate (CAGR) of around 10% by 2032. More and more engineers will be adopting FPGAs due to their versatility, acceleration capability, power efficiency and lower non-recurring engineering (NRE) costs (compared to ASICs).… High-Performance RTL Simulation Workflow with Vivado and Active-HDL |
0 events,
|
0 events,
|
|
0 events,
|
0 events,
|
0 events,
|
1 event,
-
Gate-level simulations (GLS) are a crucial step in the verification of an ASIC/FPGA. GLS is used for verifying power-up, reset operation, timing, multi-cycle paths, and power estimation. However, GLS can be a bottleneck in the project cycle due to its complexity. The nature of a GLS can cause simulations to run much longer than the… Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification |
2 events,
-
Learn How STMicroelectronics Silicon Carbide (SiC) Research Team uses Silvaco TCAD to Analyze the Impact of Surface Defect Dot on Short Circuit Phenomena in SiC Devices During SiC device switching operations, it is possible that devices could be reaching abnormal overload conditions, which is why some applications require “robustness” specifications (e.g., Short Circuit and UIS… Analyze the Impact of Surface Defect Dot on Short Circuit Phenomena in SiC Devices
-
Based on recent industry research, the FPGA market was valued at approximately USD 7.5 Billion in 2023, with an expected compound annual growth rate (CAGR) of around 10% by 2032. More and more engineers will be adopting FPGAs due to their versatility, acceleration capability, power efficiency and lower non-recurring engineering (NRE) costs (compared to ASICs).… High-Performance RTL Simulation Workflow with Quartus and Active-HDL |
0 events,
|
0 events,
|
|
0 events,
|
0 events,
|
1 event,
-
*Work email required for registration* Don't miss out on this exclusive opportunity to stay ahead in the rapidly evolving landscape of chip design. Join us for an engaging discussion that promises to inspire and inform: - Gain insights into the latest trends shaping chip design. - Learn from industry leaders about the strategies behind successful… RISC-V Instruction Set Architecture: Enhancing Computing Power |
2 events,
A pioneer and leading interdisciplinary conference, the 25thInternational Symposium on Quality Electronic Design (ISQED'24) accepts and promotes original and unpublished papers related to the topics shown below. ISQED'24 theme is AI/ML& Electronic Design, Hardware Security, Quantum Computing, 3D Integration, and IoT. Authors are invited to submit papers in following topics (please visit the website for… ISQED Symposium 2024 
Engineer a smarter future, faster at Siemens EDA User2User Conference April 3-4, 2024 Santa Clara, CA. Join your colleagues from around the industry for a day of technical sessions, networking, keynote sessions, labs and more. User2User is free of charge for Siemens EDA customers and includes sessions, lunch, and parking. Technology tracks covering the latest… Siemens EDA User2User Conference |
5 events,
-
Find out how the Virtuoso Layout Suite XL you’ve known for many years is setting new standards in custom layout authoring. The connectivity-driven paradigm keeps the layout in synch with the circuit design and ensures that the design intents are always honored. Learn how we strengthened the layout editor in Virtuoso Studio, launched in 2023,… Maximizing the Benefits of Virtuoso Layout Suite XL
-
Identifying sources of electromagnetic (EM) coupling and safeguarding today’s complex electronic designs from EM crosstalk are daunting tasks. For designs with multiple levels of hierarchy, identification, and detailed analysis of the “EM-sensitive” content is a challenge. The manual creation of wrapper cells or new layout views to enable this quickly becomes a time-consuming and error-prone… Hierarchical Analysis of EM Crosstalk with EMX Planar 3D Solver
-
Based on recent industry research, the FPGA market was valued at approximately USD 7.5 Billion in 2023, with an expected compound annual growth rate (CAGR) of around 10% by 2032. More and more engineers will be adopting FPGAs due to their versatility, acceleration capability, power efficiency and lower non-recurring engineering (NRE) costs (compared to ASICs).… High-Performance RTL Simulation Workflow with Libero and Active-HDL |
1 event,
|
0 events,
|