CXL
How Synopsys Interface IP and Arm Interoperate to Accelerate System IO and Memory Performance
In this webinar, Synopsys and Arm describe how their recent collaboration helps maximize system performance and shorten Arm-based SoC design cycles. Learn how to minimize HPC/data center SoC design risk and ensure end-to-end IP integration, using available Arm reference designs and interoperability reports. Find out how Synopsys’ interface IP for the most widely used protocols… Read More »How Synopsys Interface IP and Arm Interoperate to Accelerate System IO and Memory Performance
Defending the Cloud: PCIe and CXL Data Security for High-Performance Computing
Cloud computing is going through a significant overhaul and continues to grow globally with increasing presence of hyperscale cloud providers for big data, high-performance computing (HPC), and analytics. In-house data centers are increasingly going off-premise, resulting in the co-location of data centers that manage and store data for companies and application developers to improve scalability… Read More »Defending the Cloud: PCIe and CXL Data Security for High-Performance Computing
CXL and IDE: Important Considerations of Protecting High Speed Interconnects
In a few short years, CXL (Compute Express Link) has evolved from an idea to a rapidly proliferating low latency interconnect standard being adopted into data centers, high performance computing, and cloud computing. However, as the adoption has increased, so has the security threat model users face. To address this, the CXL 2.0 standard has… Read More »CXL and IDE: Important Considerations of Protecting High Speed Interconnects
Boost Your CXL Verification from IP to System Level
Register now for this CadenceTECHTALK, where we will walk you through CXL verification challenges from IP level to system level and demonstrate how these challenges can be significantly mitigated using the Cadence® Verification IP (VIP) solution for advanced verification methodologies. Specifically, this webinar will cover following topics: Growing market needs for CXL Verification challenges of… Read More »Boost Your CXL Verification from IP to System Level
Rambus Design Summit 2022
Join us at Rambus Design Summit Back for its third year, the Rambus Design Summit is a virtual conference focused on the selection and implementation of chip and IP solutions for the data center, edge, automotive and IoT devices including the acceleration and security of AI/ML applications. Hear our technology leaders give their insights on… Read More »Rambus Design Summit 2022
Protocol and Memory Interface Verification in the Shrinking World of 3DIC
Emerging 2.5D and 3DIC packaging technologies enable more design complexity, and bring some new verification challenges. We look at how to scale your verification capability to match and how to plan ahead for verification of die-to-die interconnect protocols such as UCIe and memory verification with HBM. Packaging technologies for 2.5D and 3DIC are becoming more… Read More »Protocol and Memory Interface Verification in the Shrinking World of 3DIC
How CXL Technology will Revolutionize the Data Center
Data Centers face many challenges in an environment of exponentially rising data volume growth. With workload demands increasing rapidly, the need for more bandwidth and capacity continues to rise. Join us for a live webinar next week on November 2nd and hear IDC guest speaker, Jeff Janukowicz, and Rambus' Mark Orthodoxou discuss how CXL technology… Read More »How CXL Technology will Revolutionize the Data Center
Rambus Design Summit 2023
Back for its fourth year, the Rambus Design Summit is a virtual conference focused on the key technologies critical to enabling performance and security for data center, AI/ML, automotive and IoT applications. Agenda + Abstracts Rambus Design Summit will take place over two days, with day one focusing on memory & interface solutions, and day… Read More »Rambus Design Summit 2023
Flash Memory Summit
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesWhy Attend Flash Memory Summit? Flash Memory Summit (FMS) is an all-inclusive international memory and storage showcase. It is the event for the memory and storage industry. It is the one-stop place to catch up on the latest technologies, see the hottest products, and learn about what's happening and where the latest trends are heading.… Read More »Flash Memory Summit
Comprehensive CXL 3.0 Verification Solution for High-Bandwidth and Low-Latency Connectivity
Join us for a deep dive into the most comprehensive CXL Verification IP solution available in the market that targets 1.1, 2.0 and 3.0, Siemens Avery CXL Verification IP. Compute Express Link (CXL) is an open industry-standard interconnect offering coherency and memory semantics using high- bandwidth, low-latency connectivity between host processor and devices such as… Read More »Comprehensive CXL 3.0 Verification Solution for High-Bandwidth and Low-Latency Connectivity