RISC-V
RISC-V Instruction Set Architecture: Enhancing Computing Power
*Work email required for registration* Don't miss out on this exclusive opportunity to stay ahead in the rapidly evolving landscape of chip design. Join us for an engaging discussion that… Read More »RISC-V Instruction Set Architecture: Enhancing Computing Power
Open Source Summit – North America
Seattle Convention Center 900 Pine Street, Seattle, WA, United StatesRegistration Cost: $15 This half day program will Introduce the audience to the many aspects of open source hardware and software development, and how it is helping the industry to accelerate… Read More »Open Source Summit – North America
Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Multi-die SoC containing multiple RISC-V clusters, GPU, NPU, accelerators and DNN have considerable benefits for applications in automotive, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect… Read More »Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Multi-die SoC containing multiple RISC-V clusters, GPU, NPU, accelerators and DNN have considerable benefits for applications in automotive, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect… Read More »Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Accelerating AI Applications Using Custom RISC-V based SIMD/VLIW DSPs
The revolution in AI triggers an increased awareness for application-specific instruction-set processors (ASIPs). These processors implement a specialized instruction-set architecture (ISA) tailored to the AI application domain, often starting from… Read More »Accelerating AI Applications Using Custom RISC-V based SIMD/VLIW DSPs
2024 ANDES RISC-V CON
The DoubleTree by Hilton 2050 Gateway Place, San Jose, CA, United StatesRecently, RISC-V, with its open, streamlined, and scalable configuration, has become the mainstream solution adopted by leading market players, paving the way for widespread technological innovation. In the RISC-V application… Read More »2024 ANDES RISC-V CON
Verification Futures Conference 2024 Austin
Austin Marriott South 4415 South Interstate 35 Frontage Road, Austin, TX, United StatesThe Verification Futures conference provides a unique blend of conference presentations, exhibitions, training and industry networking sessions dedicated to discussing the challenges faced in hardware and software verification. Verification Futures… Read More »Verification Futures Conference 2024 Austin