Coverage is an essential part of any verification environment. Coverage can be simple as a statement and branch coverage, or it can be more complex as a covergroup with constrained-random tests. Implementation, collection and analysis…
Assertion-based verification (ABV) enables the use of assertions for the efficient verification of low-level design properties. These assertions could be verified by simulation and formal verification methods. The VHDL 2008 standard includes Property Specification language…
Most FPGA designs contain configurable hard IP blocks supplied by FPGA vendors. These Hard IP blocks do not contain synthesizable RTL code, and therefore are excluded from advanced linting. In fact, this is a correct…
OSVVM has grown tremendously over the last couple of years. This period saw simulator independent scripting, test reporting, model independent transactions, virtual transaction interfaces, and additional verification components, each added and incrementally improved. We have…
According to the 2020 Wilson Verification Survey FPGA verification engineers spend 46% of their time debugging. As a result, we need good scripting to simplify running tests and good reports to simplify debug and help…
Some methodologies (or frameworks) are so complex that you need a script to create the initial starting point for writing verification components, test cases, and/or the test harness. SystemVerilog + UVM is certainly like this.…
The Open Component Portability Infrastructure (OpenCPI) is an open source software (OSS) framework for developing and executing component-based applications on heterogeneous systems. By targeting heterogeneous systems, the framework supports development and execution across diverse processing…
Functional coverage is often mentioned together with constrained-random verification, and this is a great combination. However, functional coverage is also very useful even if you have no randomization at all. This is a great method…
OSVVM is an advanced verification methodology that defines a VHDL verification framework, verification utility library, verification component library, and a scripting flow that simplifies your FPGA verification projects from start to finish. Using these libraries,…
Randomization is very important for modern verification. Still, very few designers apply randomization sufficiently in their testbenches. This means they are missing out on a very important method for finding potential bugs in their design,…