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Cadence, May 12, 2022

Tackling Advanced Analog FinFET Back-End Design Challenges

The layout implementation of analog circuits in advanced FinFET technologies is becoming increasingly complex and challenging, with many new design rules to consider and multi-patterning, density rules, matching, and EM-IR concerns. These challenges can translate… 

Cadence, May 5, 2022

Tackling Advanced Analog FinFET Front-End Design Challenges with Better Methodologies

Analog engineers adopting advanced FinFET technologies face many challenges that were not present when using planar transistors. Challenges in layout implementation have a direct impact on design specifications, and the luxury of over-margining is long… 

Cadence, May 4, 2022

Signal and Power Integrity Analysis with Sigrity Aurora

Join Cadence Training and Principal Application Engineer Vladimir Papic for this free technical Training Webinar. Cadence® Sigrity™ Aurora is a signal and power integrity (SI/PI) analysis solution, tightly integrated into the Allegro® PCB design environment.…