IP
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Compare Performance-power of Arm Cortex vs RISC-V for AI applications
In the Webinar, we will show you how to construct, simulate, analyze, validate, and optimize an architecture model using pre-built components. We will compare micro and application benchmarks on system SoC models containing clusters of ARM Cortex A53/A77/A65AE/N1, SiFive u74, and other vendor cores. Aside from the processor resources such as cache and memory, the… Compare Performance-power of Arm Cortex vs RISC-V for AI applications
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DVCon Europe 2021
The Design and Verification Conference in Europe (DVCon Europe) is the leading European event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative, DVCon Europe brings chip architects, design and verification engineers, and IP integrators the latest methodologies, techniques,… DVCon Europe 2021
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Silvaco UseRs Global Event – Japan
開催日時：2021/11/02 13:00 SURGE (Silvaco UseRs Global Event)とは、シルバコが開催するワールドワイドのイベントです。 SURGEは、TCAD、EDA、IPの各分野において、新しい技術について議論し、ユーザの経験を共有し、先進的な半導体設計のための革新的な技術を発見するためのイベントです。 本年は、オンラインでの開催となります。 当日ご参加いただき、アンケートにご回答いただいたお客様の中から抽選で50名の方にAmazonギフト券1000円分(Eメールタイプ)を進呈させていただきます。 この機会に是非ともSURGE Japanにご登録ください。
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Boost LPDDR5 Verification from IP to System Level
Overview Low power DRAM is being adopted in a wide array of markets, including automotive, PCs and networking systems built for 5G and AI applications. The specification complexity is increasing to meet higher bandwidth, better performance and extended latencies for multiple use cases. Ensuring that JEDEC low-power double data rate 5 (LPDDR5) specification and overall… Boost LPDDR5 Verification from IP to System Level
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CXL and IDE: Important Considerations of Protecting High Speed Interconnects
In a few short years, CXL (Compute Express Link) has evolved from an idea to a rapidly proliferating low latency interconnect standard being adopted into data centers, high performance computing, and cloud computing. However, as the adoption has increased, so has the security threat model users face. To address this, the CXL 2.0 standard has… CXL and IDE: Important Considerations of Protecting High Speed Interconnects
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RISC-V Days Tokyo Autumn 2021
RISC-V Days Tokyo is Japan’s largest RISC-V event. We will hold live and online presentations, live exhibition booths, and press conferences. RISC-V Days Tokyo brings together excellent RISC-V-related technologies and products, as well as key persons and engineers, and provides business opportunities such as raising product awareness, realizing collaboration between companies, technology exchange, and information… RISC-V Days Tokyo Autumn 2021
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CadenceTECHTALK: Power and Energy Optimization Using Tensilica IP
Join us as Cadence experts describe common challenges and solutions in creating an efficient and accelerated flow that will meet technical requirements for accurately measuring the power, energy, and system performance while making essential design tradeoffs to meet your aggressive time-to-market schedule. In this CadenceTECHTALK, you will learn how to: Address the challenges of accelerating… CadenceTECHTALK: Power and Energy Optimization Using Tensilica IP
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Samsung SAFE Forum 2021
Join us for Samsung Foundry’s annual SAFE™ Forum. What will you take away from Samsung Foundry’s ecosystem event? Bump your SoC PPA knowledge with the latest information on: High speed interconnect IPs for HPC and Data Center applications and foundational IPs High bandwidth memory subsystems Key IP trends for automotive and mobile applications Foundational Analog… Samsung SAFE Forum 2021
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IP-SoC Conference 21
IP-SoC 2021 will be the 24th edition of the working conference fully dedicated to IP (Silicon Intellectual Property) and IP based electronic systems. The event is the annual opportunity for IP providers and IP consumers to share information about technology trends, innovative IP SoC products, Breaking IP/SoC News, Market evolution and more. The Grenoble event is… IP-SoC Conference 21
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How to Sign Off a 10 Billion+ Transistor Design in the Cloud
Advanced semiconductor applications such as artificial intelligence / machine learning (AI/ML) and graphic processing units (GPUs) fully leverage dense, advanced-node technology to push the extreme limits of design size. To signoff such large designs, engineers are increasingly relying on distributed compute methods to accelerate the signoff analysis. Furthermore, given lack of scalability of on-premises compute… How to Sign Off a 10 Billion+ Transistor Design in the Cloud
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58th Design Automation Conference
Moscone Center 747 Howard Street, San Francisco, CA, United StatesThe Design Automation Conference (DAC) is the premier event devoted to the design and design automation of electronic systems and circuits. DAC focuses on the latest methodologies and technology advancements in electronic design. The 58th DAC will bring together researchers, designers, practitioners, tool developers, students and vendors.
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PCIe 6.0 From IP to Interconnect in High-Performance Computing
ABSTRACT: PCI Express (PCIe) is one of the most popular interface technologies in the world. Interconnects for high-performance computing (HPC) in the data center, cloud and AI edge continue to increase in speed and density. System architects, SoC designers, PCB developers and SI engineers are challenged as never before to implement bleeding edge solutions. In… PCIe 6.0 From IP to Interconnect in High-Performance Computing