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Embedded Applications Get a Helping Hand: Extensible Processor Architectures
Industry consolidation and cost streamlining eliminated many proprietary processor architectures and channeled alignment to a subset of standardized instruction set architectures (ISAs). Today, many embedded applications such as those found… Embedded Applications Get a Helping Hand: Extensible Processor Architectures
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Customers Discuss Their Real World Use of High-Level Synthesis
Summary The focus of this seminar is to have real-world customers present their successes using Catapult High-Level Synthesis (HLS) in markets such as Automotive, 5G/Communications, Video/Imaging, AI/ML, and MEMs Sensors.… Customers Discuss Their Real World Use of High-Level Synthesis
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CadenceLIVE 2022 – Silicon Valley
Cadence San Jose, CA, United StatesAre you driving design change or feel you’ve overcome challenges that could impact the electronic revolution? CadenceLIVE™ offers you an opportunity to tell your story. Showcase your expertise and offer… CadenceLIVE 2022 – Silicon Valley
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From Virtual ECU to Real Vehicle: Continuous Testing of Functional Requirements
Today, most of the software functions in a car can be tested efficiently using virtual ECU models and DevOps engineering methods. However, final acceptance tests with real vehicles are still… From Virtual ECU to Real Vehicle: Continuous Testing of Functional Requirements
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How to Eliminate Image Retention Issues with SmartSpice Flex Modeling
Image retention is a long-standing issue in the display community. To effectively solve this issue, or even to minimize its impact on their products, display manufacturers and consumer electronics vendors… How to Eliminate Image Retention Issues with SmartSpice Flex Modeling
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5X Faster Equivalence Checking with Formality ML-driven DPX
Synopsys’ Fusion Compiler provides a broad spectrum of aggressive optimization techniques such as retiming, multibit banking and advanced data-path optimization that our designers want to take advantage of to achieve… 5X Faster Equivalence Checking with Formality ML-driven DPX
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Better FPGA Verification with VHDL – Faster than “Lite” Verification Component Development with OSVVM
Some methodologies (or frameworks) are so complex that you need a script to create the initial starting point for writing verification components, test cases, and/or the test harness. SystemVerilog +… Better FPGA Verification with VHDL – Faster than “Lite” Verification Component Development with OSVVM
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2022 IEEE SYMPOSIUM ON VLSI TECHNOLOGY AND CIRCUITS
Hilton Hawaiian Village 2005 Kālia Rd, Honolulu, HI, United StatesIn-person with on-demand content The 2022 IEEE Symposium on VLSI Technology and Circuits will be organized as a hybrid event with both live sessions on-site in the Hilton Hawaiian Village… 2022 IEEE SYMPOSIUM ON VLSI TECHNOLOGY AND CIRCUITS
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ASYNC 2022 Summer School: Gate-level Design
The steering committee of the IEEE ASYNC symposium is organizing a summer school on asynchronous design. The goal of the school is to teach asynchronous chip design to students and… ASYNC 2022 Summer School: Gate-level Design
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Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows
System designers face increasing challenges to meet technical specification and time-to-market requirements. While process nodes continue to shrink, the complexity of packages continue to grow. Large pin counts of flipped… Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows
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How Static and Dynamic IR Drop Analysis Can Help PCB Designs Challenges
As boards become smaller and faster, the environment for thermal issues becomes increasingly challenging. The thermal management of significant resistive losses in PCB and package structures is critical, especially because… How Static and Dynamic IR Drop Analysis Can Help PCB Designs Challenges
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Functional Verification to Fault Simulation: Considerations and Efficient Bring-Up
Electronic systems in automobiles are growing rapidly in size, complexity, and critical functionality. As a result, functional safety verification is emerging as an essential requirement for automotive SoC and IP… Functional Verification to Fault Simulation: Considerations and Efficient Bring-Up
12 events found.