System planning is a major part of multi-chiplet design. Whether it’s a 2.5-D configuration with an interposer or full-stacked 3D design mounted on a package, it is important to have an automated way to do bump assignment and optimization along with 3D structures implementation. With methodology evolving for different types of designs, a top-down and… Read More »CadenceTECHTALK: System Planning and Implementation for Different 3D-IC Design Styles

A 3D-IC includes the package, interposer, multiple chiplets, through-silicon vias (TSVs), and through-dielectric vias (TDVs). Supplying power to the chiplets and dissipating heat through these various components poses a major power integrity (PI) and thermal integrity challenge. Early analysis is extremely critical in 3D-ICs, since changing the die stack up later in the design process… Read More »CadenceTECHTALK: 3D-IC Chip-Centric Power and Thermal Integrity with High-Performance Hierarchical Analysis

Electronic products with 3D-ICs face growing system challenges related to signal, power, and thermal integrity. Design density can lead to performance issues caused by heat, crosstalk, and power noise. In this session, we will address these concerns through simulation during system planning and continuing through signoff to accelerate the 3D-IC design cycle and avoid expensive… Read More »CadenceTECHTALK: Overcoming System-Level 3D-IC Electrical and Thermal Challenges