3D IC
3DIC 2021
North Carolina State University 1101 Garman St., Raleight, NC, United StatesIEEE International 3D System Integration Conference (3DIC) November 15-18, 2021 Raleigh, North Carolina, USA After a one-year hiatus, 3DIC will once again unite 2.5D/3D researchers and developers from all around the world. This year’s conference employs a hybrid format of in-person events and virtual events. Talks, panels, exhibits, papers, and discussions will foster a stimulating… Read More »3DIC 2021
CadenceTECHTALK: Efficient Multi-Chiplet Design with Integrity 3D-IC Unified Platform
Multi-chiplet design and packaging introduces extra design and analysis requirements like system planning, bump alignment, TSV and micro-bump insertion and extraction, electrothermal analysis, cross-die STA, and inter-die physical verification, which must be considered early during planning and implementation. The new Cadence® Integrity™ 3D-IC platform provides innovative technology that proactively looks ahead through integrated planning, implementation,… Read More »CadenceTECHTALK: Efficient Multi-Chiplet Design with Integrity 3D-IC Unified Platform
CadenceTECHTALK: System Planning and Implementation for Different 3D-IC Design Styles
System planning is a major part of multi-chiplet design. Whether it’s a 2.5-D configuration with an interposer or full-stacked 3D design mounted on a package, it is important to have an automated way to do bump assignment and optimization along with 3D structures implementation. With methodology evolving for different types of designs, a top-down and… Read More »CadenceTECHTALK: System Planning and Implementation for Different 3D-IC Design Styles
CadenceTECHTALK: 3D-IC Chip-Centric Power and Thermal Integrity with High-Performance Hierarchical Analysis
A 3D-IC includes the package, interposer, multiple chiplets, through-silicon vias (TSVs), and through-dielectric vias (TDVs). Supplying power to the chiplets and dissipating heat through these various components poses a major power integrity (PI) and thermal integrity challenge. Early analysis is extremely critical in 3D-ICs, since changing the die stack up later in the design process… Read More »CadenceTECHTALK: 3D-IC Chip-Centric Power and Thermal Integrity with High-Performance Hierarchical Analysis
CadenceTECHTALK: Overcoming System-Level 3D-IC Electrical and Thermal Challenges
Electronic products with 3D-ICs face growing system challenges related to signal, power, and thermal integrity. Design density can lead to performance issues caused by heat, crosstalk, and power noise. In this session, we will address these concerns through simulation during system planning and continuing through signoff to accelerate the 3D-IC design cycle and avoid expensive… Read More »CadenceTECHTALK: Overcoming System-Level 3D-IC Electrical and Thermal Challenges
Signal Integrity Issues for Silicon Interposers
The development of applications like high-performance computing, Artificial Intelligence (AI) processors, and Central Processing Unit (CPU) and Graphical Processing Unit (GPU) chips involves advanced packaging technologies that radically alter traditional design methodologies and flows. Designers of high-speed components are called to co-simulate die, interposers, and package to sign off for their products' signal integrity (SI)… Read More »Signal Integrity Issues for Silicon Interposers
Thermal Integrity Challenges and Solutions of Silicon Interposer Design
In this latest installment of the year-long 3D-IC webinar series, Dr. Lang Lin will discuss the Thermal Integrity issues associated with 3D-IC designs. The presentation will cover thermal hotspots, mechanical stresses induced by thermal issues, and methods for capturing these problems with simulation and virtual prototyping, with a focus on designs that utilize silicon interposers.… Read More »Thermal Integrity Challenges and Solutions of Silicon Interposer Design
Siemens Tessent DFT Forum 2023 India
Hotel Radisson Blu Marathalli ORR, Bengaluru, IndiaAbout Siemens Tessent DFT Forum 2023 India Presenting silicon lifecycle solutions from Siemens EDA: Engineering a smarter future faster Join us for the Siemens Tessent Design-for-Test (DFT) India Tech Forum, being held in Hotel Radisson Blu, Marathalli ORR, Bengalur India, on 29th March, 2023 learn from Industry leaders, fellow designers and experts from Siemens about how to leverage the Tessent… Read More »Siemens Tessent DFT Forum 2023 India
Power Integrity Issues and Solutions for Silicon Interposers
Join us on May 17 for the latest 3D-IC webinar series, “Power Integrity Challenges and Solutions for Interposer Design.” The discussion will focus on interposer power analysis as an isolated case and in context with the dice instantiated in a 3D-IC device. The presentation will then explore the completed multi-chip design in a system simulation.… Read More »Power Integrity Issues and Solutions for Silicon Interposers
3D-IC Foundry Frameworks
Join us on July 20th; Ansys R&D members will discuss an overview of the 3D-IC technology development frameworks offered by TSMC, Samsung, and Intel and how Ansys simulation tools and workflows fit into those frameworks. About this Webinar Semiconductor applications such as Mobile (5G), Automotive, and Datacenter (HPC, AI) demand better scaling, performance, and lower… Read More »3D-IC Foundry Frameworks
Solution for 3D-IC Interposer Signal Integrity
Our upcoming CadenceTECHTALK: Solution for 3D-IC Interposer Signal Integrity is designed to teach engineers to translate a GDSII stream format (GDSII) file and partition it into simulation blocks for the Clarity 3D field solver. First, you will learn to use GDS-supporting files to simplify GDS to SPD translation and reuse those files to make the… Read More »Solution for 3D-IC Interposer Signal Integrity