Some methodologies (or frameworks) are so complex that you need a script to create the initial starting point for writing verification components, test cases, and/or the test harness. SystemVerilog + UVM is certainly like this.… Better FPGA Verification with VHDL – Faster than “Lite” Verification Component Development with OSVVM
Functional coverage is often mentioned together with constrained-random verification, and this is a great combination. However, functional coverage is also very useful even if you have no randomization at all. This is a great method… FPGA Design/Verification: Code, Functional and Specification Coverage
The Xilinx Versal ACAP platform is multi-featured, offering unprecedented system level performance and integration. This informative workshop (delivered in 2 half day sessions) is a comprehensive and practical introduction to the features and capabilities. We’ll… Versal ACAP Workshop Online
Randomization is very important for modern verification. Still, very few designers apply randomization sufficiently in their testbenches. This means they are missing out on a very important method for finding potential bugs in their design,… FPGA Design/Verification: Randomization
Presenter: Espen Tallaksen, CEO of EmLogic Thursday, May 5, 2022 Abstract: For most FPGA projects, over 50% of the overall project time is spent on verification. This time can be significantly reduced if the verification… FPGA Verification Architecture Optimization with UVVM
Designing FPGAs that use a single clock domain is a luxury that very few of us have. Modern FPGA designs must cope with multiple clocks running at different frequencies, very often asynchronous to each other,… Running CDC Analysis with Xilinx Parameterized Macros
The FPGA design architecture is the single most important and primary factor in achieving development efficiency, quality and reliability. The difference between a good and a bad design architecture can be about 50% of the… Webinar: FPGA Design Architecture Optimization
Requirements-based verification (RBV) is a popular verification process for FPGA designs used in safety-critical systems. The effectiveness of RBV is limited by the quality and precision of the requirements. Verification techniques such as constrained random… Using SVA for Requirements-Based Verification of Safety-Critical FPGA Designs
In this webinar, we will present the open-source FPGA tools which automate the tapeout flow for custom FPGA fabrics. We will cover the key steps involved in the process when using the tools, including netlist… Open-Source FPGA: Towards Fully Automated FPGA Tapeout Flows
