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Mirabilis, October 15, 2024

ARM corelink, Arteris NoC, UCIe, Bunch-of-wires, CXL and PCIe- Designing the interconnect is not for the weak-hearted

There are so many options for Network-on-Chip: ARM-Corelink CMN700, Arteris FlexNoC, open-source NoC interconnect, and of course developing home-grown fully customized solutions. Where does each solution fit? Where do we use it- backplane vs inside… ARM corelink, Arteris NoC, UCIe, Bunch-of-wires, CXL and PCIe- Designing the interconnect is not for the weak-hearted

Keysight, February 28, 2024

Keysight EDA Connect World Tour: Santa Clara – High Speed Digital

Shift Left with the Modern Design Center Artificial intelligence (AI) is redefining high-speed digital designs. Your ability to design, simulate, and test — using an automated, integrated workflow — is what will set you apart.… Keysight EDA Connect World Tour: Santa Clara – High Speed Digital

Siemens, January 24, 2024

Comprehensive PCIe Verification Solution for bleeding edge and mission critical SoC & IP Designs

Applications such as Data Centers, High-Performance computing (HPC), artificial intelligence/machine learning (AI/ML), cloud computing, military, and aerospace, automotive, etc. are all extremely Bandwidth-hungry. To cater to such high demands of high speeds and bandwidth requires… Comprehensive PCIe Verification Solution for bleeding edge and mission critical SoC & IP Designs

Mirabilis, October 27, 2022

Evaluating UCIe based multi-die architectures to meet timing and power constraints

Multi-die architectures have evolved from proprietary to industry standard UCIe.  UCIe can accommodate the bulk of designs today from 8 Gbps per pin to 32 Gbps per pin for high-bandwidth applications from networking to Hyperscale… Evaluating UCIe based multi-die architectures to meet timing and power constraints

Synopsys, July 14, 2022

Overcoming PCIe 6.0 System Integration and Pre-Silicon Validation Challenges

PCIe, the most popular interconnect in compute, AI and storage systems, is now offering faster data rate, higher performance, lower power and lower latency than the previous generation. Because of these reasons and the addition… Overcoming PCIe 6.0 System Integration and Pre-Silicon Validation Challenges

Aldec, February 10, 2022

Verification of PCIe-based FPGA Designs Requiring DO-254 Compliance (US)

PCIe-based FPGA designs are becoming popular within avionics systems. However, the verification of such designs for DO-254 compliance with design assurance level (DAL) A or B is problematic. FPGA designs that use asynchronous clocks with… Verification of PCIe-based FPGA Designs Requiring DO-254 Compliance (US)

synopsys, december 8, 2021

PCIe 6.0 From IP to Interconnect in High-Performance Computing

ABSTRACT: PCI Express (PCIe) is one of the most popular interface technologies in the world. Interconnects for high-performance computing (HPC) in the data center, cloud and AI edge continue to increase in speed and density.… PCIe 6.0 From IP to Interconnect in High-Performance Computing

rambus siemens

CXL and IDE: Important Considerations of Protecting High Speed Interconnects

In a few short years, CXL (Compute Express Link) has evolved from an idea to a rapidly proliferating low latency interconnect standard being adopted into data centers, high performance computing, and cloud computing. However, as… CXL and IDE: Important Considerations of Protecting High Speed Interconnects

Defending the Cloud: PCIe and CXL Data Security for High-Performance Computing

Defending the Cloud: PCIe and CXL Data Security for High-Performance Computing

Cloud computing is going through a significant overhaul and continues to grow globally with increasing presence of hyperscale cloud providers for big data, high-performance computing (HPC), and analytics. In-house data centers are increasingly going off-premise,… Defending the Cloud: PCIe and CXL Data Security for High-Performance Computing