Webinar
Compare Performance-power of Arm Cortex vs RISC-V for AI applications
In the Webinar, we will show you how to construct, simulate, analyze, validate, and optimize an architecture model using pre-built components. We will compare micro and application benchmarks on system… Read More »Compare Performance-power of Arm Cortex vs RISC-V for AI applications
Using OVL for Assertion-based Verification of Verilog and VHDL Designs
Open Verification Library (OVL) is a library of property checkers for digital circuit descriptions written in popular Hardware Description Languages and maintained by Accelera. The OVL checkers could be used… Read More »Using OVL for Assertion-based Verification of Verilog and VHDL Designs
Managing SoC Subsystems and Other Hierarchy With Methodics IPLM
For the past 10+ years, semiconductor design has moved from a project-based "start again" mindset to a more modular, "IP-centric" approach. This has significantly reduced project cost and improved time-to-market… Read More »Managing SoC Subsystems and Other Hierarchy With Methodics IPLM
Xcelium ML for 5X Faster Regression Throughput
Overview Regressions time often becomes one of the biggest challenges to meet the tight project schedule with increasing complexity of the SoC designs and shorter time to market. Verification engineers… Read More »Xcelium ML for 5X Faster Regression Throughput
Intelligent Cross-Platform Workflows for RF PCB Integration
The last webinar in The Cadence® AWR® V16 for RF Design Excellence Webinar Seriesintroduces groundbreaking cross-platform workflows from AWR® software to Allegro® PCB Designer, which help to deliver up to… Read More »Intelligent Cross-Platform Workflows for RF PCB Integration
Understanding Random Stability in SystemVerilog and UVM
Webinar Overview: A common issue with constrained random simulation is being able to reproduce random stimulus for debug purposes and for locking down regressions test suites. This is especially problematic… Read More »Understanding Random Stability in SystemVerilog and UVM
Constraint Random Verification with Python and Cocotb
Abstract: Testing digital hardware has never been an easy job, and it won’t get easier any time soon. But that doesn’t mean writing test code can’t be enjoyable and productive!… Read More »Constraint Random Verification with Python and Cocotb
Boost LPDDR5 Verification from IP to System Level
Overview Low power DRAM is being adopted in a wide array of markets, including automotive, PCs and networking systems built for 5G and AI applications. The specification complexity is increasing… Read More »Boost LPDDR5 Verification from IP to System Level
CXL and IDE: Important Considerations of Protecting High Speed Interconnects
In a few short years, CXL (Compute Express Link) has evolved from an idea to a rapidly proliferating low latency interconnect standard being adopted into data centers, high performance computing,… Read More »CXL and IDE: Important Considerations of Protecting High Speed Interconnects
Workforce Shortages—Meeting Challenges for the Semiconductor Industry
As demand for semiconductors is increasing, foundries and other makers of chips are expanding their manufacturing capacities. With new fabs bringing thousands of new jobs to the US, Texas is… Read More »Workforce Shortages—Meeting Challenges for the Semiconductor Industry
Virtual Prototyping Day – Silver: Accelerate Your Innovation with Virtual ECUs
Synopsys invites you to the Virtual Prototyping Day – Silver, a virtual event on virtual ECUs and applications in automotive software development. Users share their experiences with the latest techniques… Read More »Virtual Prototyping Day – Silver: Accelerate Your Innovation with Virtual ECUs
Enabling Effective Design & Layout Collaboration for Next Generation Analog and Mixed-Signal Designs
Analog designers appreciate the importance of tight communication between layout and design teams, yet with geographically dispersed teams this can be a big challenge. Close collaboration between circuit designer and… Read More »Enabling Effective Design & Layout Collaboration for Next Generation Analog and Mixed-Signal Designs