Webinar
Effectively Addressing the Challenge of Securing Connected and Autonomous Vehicles
Overview As vehicles get more complex and connected, the attack surface increases. This presents increasing challenges for cybersecurity. This webinar introduces hardware based techniques for addressing security concerns, from legacy through to the future. What will you learn? The best use of threat modelling techniques Methods for staying one step ahead of malicious hackers in… Read More »Effectively Addressing the Challenge of Securing Connected and Autonomous Vehicles
Entering a New Era with Linux-Based Automotive Software-in-the-Loop Test Tools
Trends such as advanced driver assistance systems (ADAS) and autonomous driving (AD) make software the differentiating factor in the automotive industry. To keep pace with innovations and to shorten development cycles, testing of electronic control units (ECUs) must shift-left. The use of software-in-the-loop (SiL) simulations is a recognized and established approach to frontload test activities to earlier development phases. Recently, automotive… Read More »Entering a New Era with Linux-Based Automotive Software-in-the-Loop Test Tools
The most error prone FPGA corner cases
Presenter: Espen Tallaksen, CEO of EmLogic Thursday, October 14, 2021 Abstract: Cycle related corner cases are probably the worst and main reason for undetected bugs on many FPGAs. To explain this in a simple way, - a cycle related corner case is for instance if you have an event counter where the number of counted… Read More »The most error prone FPGA corner cases
Defending the Cloud: PCIe and CXL Data Security for High-Performance Computing
Cloud computing is going through a significant overhaul and continues to grow globally with increasing presence of hyperscale cloud providers for big data, high-performance computing (HPC), and analytics. In-house data centers are increasingly going off-premise, resulting in the co-location of data centers that manage and store data for companies and application developers to improve scalability… Read More »Defending the Cloud: PCIe and CXL Data Security for High-Performance Computing
Advanced Antenna Design and Integration Through Circuit/EM Co-Simulation
The Cadence® AWR® V16 for RF Design Excellence Webinar Series introduces the latest capabilities in Cadence® AWR Design Environment® Version 16 (V16), providing ready access to Cadence Clarity™ 3D Solver and Celsius™ Thermal Solver for unconstrained capacity to solve large-scale and complex RF systems directly from within the RF design platform. Our next webinar in… Read More »Advanced Antenna Design and Integration Through Circuit/EM Co-Simulation
Python in Verification Online Meetup
Veriest is inviting you to another event in our series of online Verification Meetups. This time, we'll have two presentations on the polemic topic of using Python in Verification, one by an industry expert and the other by one of Veriest technical leaders. Save the date and watch this space for more details!
Compare Performance-power of Arm Cortex vs RISC-V for AI applications
In the Webinar, we will show you how to construct, simulate, analyze, validate, and optimize an architecture model using pre-built components. We will compare micro and application benchmarks on system SoC models containing clusters of ARM Cortex A53/A77/A65AE/N1, SiFive u74, and other vendor cores. Aside from the processor resources such as cache and memory, the… Read More »Compare Performance-power of Arm Cortex vs RISC-V for AI applications
Using OVL for Assertion-based Verification of Verilog and VHDL Designs
Open Verification Library (OVL) is a library of property checkers for digital circuit descriptions written in popular Hardware Description Languages and maintained by Accelera. The OVL checkers could be used not only in dynamic simulation, but also in formal verification and emulation. Also, the OVL-based verification technology provides the easiest way for designers to implement… Read More »Using OVL for Assertion-based Verification of Verilog and VHDL Designs
Managing SoC Subsystems and Other Hierarchy With Methodics IPLM
For the past 10+ years, semiconductor design has moved from a project-based "start again" mindset to a more modular, "IP-centric" approach. This has significantly reduced project cost and improved time-to-market by encouraging the outsourcing of niche areas of the design to specialists, enabling the use of foundry sourced IP (often for free) and emphasizing the… Read More »Managing SoC Subsystems and Other Hierarchy With Methodics IPLM
Xcelium ML for 5X Faster Regression Throughput
Overview Regressions time often becomes one of the biggest challenges to meet the tight project schedule with increasing complexity of the SoC designs and shorter time to market. Verification engineers apply a coverage-driven methodology and run a large number of constrained random tests with multiple seeds in massive regressions to meet their coverage goals. Thus,… Read More »Xcelium ML for 5X Faster Regression Throughput
Intelligent Cross-Platform Workflows for RF PCB Integration
The last webinar in The Cadence® AWR® V16 for RF Design Excellence Webinar Seriesintroduces groundbreaking cross-platform workflows from AWR® software to Allegro® PCB Designer, which help to deliver up to a 50% reduction in turnaround time compared to competing solutions. RF IP integration within a larger mixed-signal PCB system is hampered by disjointed workflows between… Read More »Intelligent Cross-Platform Workflows for RF PCB Integration
Understanding Random Stability in SystemVerilog and UVM
Webinar Overview: A common issue with constrained random simulation is being able to reproduce random stimulus for debug purposes and for locking down regressions test suites. This is especially problematic when the source code needs to be modified and is known in SystemVerilog as random stability. In this webinar, we explain: Random stability in SystemVerilog… Read More »Understanding Random Stability in SystemVerilog and UVM