Webinar
LIVE WEBINAR: How to Simplify the Verification of Bus Interfaces (US)
Abstract: Today’s FPGAs and SoC FPGAs use various types of bus interconnect - such as AXI, APB, AHB, Avalon or Wishbone - for both internal (IP-level) and external communication. A… Read More »LIVE WEBINAR: How to Simplify the Verification of Bus Interfaces (US)
Ensuring Standards Compliance: Automating Post-Route Analysis for Hundreds of Serial Links
Presented by Todd Westerhoff, Product Marketing Manager for High-Speed System Design, Siemens EDA Abstract The PCB layout team has just handed you back a routed database with hundreds of serial… Read More »Ensuring Standards Compliance: Automating Post-Route Analysis for Hundreds of Serial Links
PCIe 6.0 From IP to Interconnect in High-Performance Computing
ABSTRACT: PCI Express (PCIe) is one of the most popular interface technologies in the world. Interconnects for high-performance computing (HPC) in the data center, cloud and AI edge continue to… Read More »PCIe 6.0 From IP to Interconnect in High-Performance Computing
Bug Tracking with Indago Interactive for Specman
Join Cadence® Training and Principal Application Engineer Daniel Bayer for this free technical training webinar. The Indago™ Debug Platform is optimized for scalability, supporting debug of simulation runs as well… Read More »Bug Tracking with Indago Interactive for Specman
How to Overcome the Pain Points of AI/ML Hardware Design
Join Achronix for a live Webinar December 16th: 10-11 AM Pacific and Recorded On-Demand After the Event AI/ML hardware faces three common pain points: memory bandwidth, computational throughput and on-chip… Read More »How to Overcome the Pain Points of AI/ML Hardware Design
Improving Design Power and Performance with RTL Architect
Exploring the impact of RTL on implementation PPA has traditionally been very difficult since it was hard to connect the results to the source code. The first difficulty occurs during elaboration… Read More »Improving Design Power and Performance with RTL Architect
A Faster Path to Analog IC Layout
Hey analog layout engineer! Start your journey in 2022 the right way, book a place in this webinar. In 'A faster path to analog layout' Mark Waller will show you… Read More »A Faster Path to Analog IC Layout
Accelerating Complex SoCs Prototyping with Protium X2
This CadenceTECHTALK will offer an overview of the Protium™ Enterprise Prototyping Platform for fast hardware and software verification. We will review the traditional prototyping challenges of complex SoCs using a… Read More »Accelerating Complex SoCs Prototyping with Protium X2
Increase your productivity with Continuous Integration flows
Abstract: In a team environment, verification engineers push code changes every day, and sometimes several times a day, to a shared repository. Each change has the potential to introduce new… Read More »Increase your productivity with Continuous Integration flows
Introduction to Questa Lint and CDC for Designers
Have you ever had RTL code that passes simulation but still fails due to things like unreachable code, out-of-range violations, or incorrect order of execution? Have you ever dealt with… Read More »Introduction to Questa Lint and CDC for Designers
Learn How to Perform Device Meshing with Silvaco’s Victory Mesh TCAD Solution
ictory Mesh is Silvaco’s TCAD solution for device meshing and solid modeling. Victory Mesh creates suitable meshes from process structures for device simulation. For example, the results produced by process… Read More »Learn How to Perform Device Meshing with Silvaco’s Victory Mesh TCAD Solution
Boost Your CXL Verification from IP to System Level
Register now for this CadenceTECHTALK, where we will walk you through CXL verification challenges from IP level to system level and demonstrate how these challenges can be significantly mitigated using… Read More »Boost Your CXL Verification from IP to System Level