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For 60 years, IRPS has been the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all other parts of the world… IRPS 2023 will be presented as an in-person conference, with a virtual component available. The… IRPS 2023 
We are happy to announce that once again the International Electrostatic Discharge Workshop (IEW) will be co-locating with IRPS this year. Their submission deadline is January 23, 2023. For further details, including the Call for Posters, please visit their webpage here. 
General Information The International Symposium on Physical Design (ISPD) provides a premier forum to exchange ideas and promote innovative research in all aspects of physical design ranging from traditional topics for ASIC and FPGA designs to emerging technologies that impact physical design of integrated circuits (ICs). In 2023, ISPD will be online with virtual participation,… International Symposium on Physical Design (ISPD) 2023 |
5 events,
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Semiconductor companies have long recognized the importance of yield management and having the right support in place to maximize results. In this 30-minute webinar brought to you by yieldHUB and SemiWiki, attendees will learn about a key to success in the world of yield management (and something that can be underestimated) - collaboration. This is… Maximizing yields through collaboration
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The ESD Alliance Export Committee will hold a seminar called “The Impact of New Regulations on the Semiconductor Design Ecosystem.” This seminar is presented by the ESD Alliance, a SEMI Technology Community, and will be hosted by Cadence Design Systems at their San Jose Headquarters. The Cadence Government and Trade Team will cover general trade compliance… ESD Alliance Export Seminar |
6 events,
Since 1991, the Synopsys Users Group (SNUG) has represented a global design community focused on innovating from Silicon to Software. Today, as the electronics industry’s largest user conference, SNUG brings together over 12,000 Synopsys tool and technology users across North America, Europe, Asia, and Japan. In addition to peer-reviewed technical presentations and insightful keynotes from… SNUG Silicon Valley 2023
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TechNES is pleased to announce the next FPGA Front Runners event – to he hosted by Leonardo at their venue in Edinburgh on March 29th, and will focus on FPGA Design using High Level Languages. The FPGA Front runners is all about bringing together the UK FPGA & ASIC design communities to discuss all things… FPGA Frontrunner Meet & Greet
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About Siemens Tessent DFT Forum 2023 India Presenting silicon lifecycle solutions from Siemens EDA: Engineering a smarter future faster Join us for the Siemens Tessent Design-for-Test (DFT) India Tech Forum, being held in Hotel Radisson Blu, Marathalli ORR, Bengalur India, on 29th March, 2023 learn from Industry leaders, fellow designers and experts from Siemens about how to leverage the Tessent… Siemens Tessent DFT Forum 2023 India |
5 events,
Standard Level - 2 sessions (4 hours per session including breaks) With thanks to AMD Xilinx for sponsoring this workshop: It is available to attend FREE OF CHARGE (Usual price $990) March 30-31 2023 - Americas - Register Now » March 30-31 2023 - EurAsia - Register Now » The Versal® Adaptive SoC from AMD Xilinx is multi-featured, offering… Versal Adaptive SoCs ONLINE WORKSHOP
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Driven by the trend towards software-defined vehicles (SDV), more complex software stacks are now being integrated into innovative automotive E/E architectures. Today the early integration testing of automotive software is already supported by using virtual ECUs (vECUs). However, the production basic software (BSW) is often not included because the virtualization of the hardware-specific microcontroller abstraction layer (MCAL)… How to Achieve Seamless Deployment of Level 3 Virtual ECUs for Automotive Digital Twins |
2 events,
The FOSSi Foundation is proud to announce Latch-Up, a conference dedicated to free and open source silicon to be held over the weekend of Friday, March 31 to Sunday, April 2, 2023 in Santa Barbara, California, USA. Latch-Up is a weekend of presentations and networking for the open source digital design community, much like its European sister conference ORConf. So… Latch-Up 2023 |
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3 events,
The 24th International Symposium on Quality Electronic Design (ISQED'23) is the premier interdisciplinary and multidisciplinary Electronic Design conference—bridges the gap among Electronic/Semiconductor ecosystem members providing electronic design tools, integrated circuit technologies, semiconductor technology,packaging, assembly & test to achieve total design quality. ISQED 2023 will held with the technical sponsorship of IEEE CASS, IEEE EDS, and in-cooperation with ACM/SigDA. Conference… ISQED 2023
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Over the last few decades System on Chip (SoC) design size has dramatically increased, and more complexity has been introduced to deliver the desired functionality. Growing design sizes lead to the introduction of several asynchronous clocks which can result in the reporting of millions of clock domain crossings (CDC) at the IP/SoC level. This leads… Shorten Your CDC Debug Cycle by 10X with ML-based RCA
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This webinar cover the modeling abstraction in the design of electronics, semiconductors and software. This webinar will definitely improve your modeling skills! --Is the abstraction right for your application and design goal? --How do you accelerate the simulation using abstraction? --Can you change the model of computation using abstraction to simplify the modeling effort? During… Choosing the best modeling abstraction for your analysis |
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Advanced semiconductor nanometer technology nodes, together with smart IC design applications enable today very complex and powerful systems for communication, automotive, data transmission, AI, IoT, medical, industry, energy harvesting, and many more. However, more aggressive time-to-market and higher performance requirements force IC designers to look for advanced and seamless design flows, tools & methodologies to… Enhance Productivity with Machine Learning in the Analog Front-End Design Flow |
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3 events,
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U2U is your opportunity to learn, grow and connect with fellow technical experts who design leading-edge products using Siemens EDA tools. U2U is focused on these areas: Analog/Mixed-Signal Verification Calibre Design Solutions & Power Integrity Analysis Digital IC Implementation Functional Design & Verification Hardware-Assisted Verification High-Level Synthesis/Verification & RTL Power Estimation/Optimization Next Gen Packaging and… User2User North America
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In this webinar we will take the comparator circuit from last time and look at how to do the layout with the 2 most used open source layout tools. We will send the link to the webinar recording to those who registered. We will cover: Creation of the transistors Layout with Magic Layout with Klayout… Analog Layout with Thomas Parry and Tim Edwards
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A logic simulator’s programming interfaces can be used for not only verifying logic IP but also the co-development of logic and embedded software. Our ‘Introducing Logic Simulator Programming Interfaces for FPGA designs’ three-part webinar series starts on April 13. Our guest presenter for this series is Simon Southwell, from Anita Simulators, and the schedule is… The Power of Verilog’s PLI and VPI for FPGA Designs |
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1 event,
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Join us for a free, half-day workshop on the key concepts of an ASIC design physical implementation flow using OpenROAD. OpenROAD delivers a fast, barrier-free, and low-cost RTL-to-GDS, no-human-in-loop flow for design above 12nm and is one of the tools students can work with in UCSC Silicon Valley Extension VLSI Engineering program courses Knowing how to use open EDA tools boosts… ASIC Design Using OpenROAD |
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3 events,
The DATE conference is the main European event bringing together designers and design automation users, researchers and vendors as well as specialists in the hardware and software design, test and manufacturing of electronic circuits and systems. DATE puts a strong emphasis on both technology and systems, covering ICs/SoCs, reconfigurable hardware and embedded systems as well… DATE 2023 
Exhibitors & Products Conference Program Networking AI & Machine Learning Carbon-neutral production Energy Management Hydrogen & Fuel Cells Industry 4.0
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Call for papers There is no doubt that proprietary EDA tools are successful, mature, and fundamental for hardware development. However, the “walled garden” approach created by closed-source tool flows can hamper novel FPGA/ASIC-based applications and EDA innovation alike by requiring that researchers either operate within the limits of what has already been imagined, or require… 3rd Workshop on Open-Source Design Automation |
4 events,
he 13th CS International conference builds on the strengths of its predecessors, with around 40 leaders from industry and academia delivering presentations that fall within five key themes: Ultrafast Communication; Making Headway with the MicroLED; Taking the Power from Silicon, New Vectors for the VCSEL, and Ultra-wide Bandgap Devices. Delegates attending these sessions will gain… CS International Conference
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Advanced Static Sign-Off Methodologies Leading SoC designers will share their advanced static sign-off methodologies and best practices to support first-silicon design goals, along with results achieved in accelerating early functional verification and sign-off of digital designs. Topics will include: AI/ML, targeted sign-off, incremental sign-off, multimode, hierarchical, dynamic CDC, and more. Advanced Static Sign-Off Methodology Presenters:… Static Sign-Off Symposium 2023 |
4 events,
Join us for CadenceLIVE™ Silicon Valley 2023, held on April 19-20 at the Santa Clara Convention Center. This annual user conference features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products. CadenceLIVE brings together users, developers, and industry experts to connect, share ideas, and inspire design creativity. Attendees have the… CadenceLIVE Silicon Valley 2023 |
3 events,
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The use of the RISC-V ISA to develop processors for SoCs is a growing trend. An important driver is the ability to customize or create ISA and micro-architectural extensions to differentiate designs across application areas including AI, machine learning, automotive, data center, mobile, and consumer. Traditionally, designing proprietary cores with the right extensions has been… Taking the Risk out of RISC-V with Fast, Architecture-Driven, PPA Optimization |
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Sponsored by IEEE and SSCS, the IEEE Custom Integrated Circuits Conference – CICC – is a premier conference devoted to IC development. The conference program is a blend of oral presentations, exhibits, panels and forums. The conference sessions present original first published technical work and innovative circuit techniques that tackle practical problems. CICC is the conference… CICC 2023 |
4 events,
The IEEE VLSI Test Symposium (VTS) explores emerging trends and novel concepts in test, validation, yield, reliability, and security of microelectronic circuits and systems. The symposium will take place on April 24-26, 2023, at the Hyatt Regency Mission Bay Spa & Marina, 1441 Quivira Road, San Diego, CA, USA. The program includes keynotes, scientific paper… 41st IEEE VLSI Test Symposium 2023 
Where the World Talks Security™ Don’t miss the opportunity to take your knowledge and skills to the next level at RSAC 2023. Not sure if the complete Conference experience will work with your schedule and budget? We offer several pass options—including an On Demand Pass. But hurry, our final discount ends Friday, April 21! In… RSAConference 2023
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Where : Hyatt Regency Santa Clara 5101 Great America Parkway, Santa Clara, CA D&R IP-SoC Silicon Valley 2023 Day is the unique worldwide Spring event fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems. IP-SoC providers, the seed of innovation in Electronic Industry, are invited to highlight their latest products and services… D&R IP-SoC Silicon Valley 2023 |
5 events,
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In today's competitive landscape for IoT, edge, and cloud solutions, User Experience (UX) design has become more crucial than ever in achieving customer and business goals. During this live webinar, we will explore how UX design affects everything from sales, customer retention, time-to-market, to internal support and development costs. We'll delve into key principles of… The ROI of User Experience Design: Increase Sales and Minimize Costs
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Discuss the performance verification challenges posed by complex SoC with distributed cache from cluster, to interconnect to die-to-die. Agenda (BST) 12:00 Welcome and Introduction – Mike Bartley, Tessolve 12:00 Nick Heaton, Cadence Design Systems - SoC Verification in a Multi-chip, Multi-die world 12:30 TBD 13:00 TBD 13:30 Close Additional Information For additional information please visit… DVClub Europe – Performance Testing and Analysis |
7 events,
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D&R IP-SoC Silicon Valley 2023 Day is the unique worldwide Spring event fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems. IP-SoC providers, the seed of innovation in Electronic Industry, are invited to highlight their latest products and services and share their vision about the next innovation steps in the Electronic Industry.… IP SoC Silicon Valley 23
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Join us and learn about: TSMC's smartphone, HPC, IoT, and automotive platform solutions TSMC's advanced technology progress on 5nm, 4nm, 3nm, 2nm processes and beyond TSMC's specialty technology breakthroughs on ultra-low power, RF, embedded memory, power management, sensor technologies, and more TSMC 3DFabric™ advanced packaging technology advancement on InFO, CoWoS®, and SoIC TSMC's manufacturing excellence,… TSMC – North America Technology Symposium
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In this event, experts from Martin-Luther-Universitat Halle Wittenberg, University of York, and Synopsys QuantumATK will present how to use ab initio DFT modeling and atomistic spin dynamics simulations of MTJs to guide and accelerate the technological development of magnetic memory such as STT and SOT-MRAM. Investigating the potential of novel magnetic tunnel junction (MTJ) materials… Advancing Magnetic Memory Technology with Atomistic Modeling |
5 events,
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This webinar will cover how using deep data analytics: Accelerates time-to-market by 20-25% (equivalent to six months in this example), ensuring the product is first to market and able to capitalize on this advantage. Reduces design and development costs by nearly $25M, amounting to a 9% cost savings. Leads to a higher quality product by improving performance by… How Deep Data Analytics Accelerates SoC Time-To-Market by 6 Months
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Today’s modern electronic designs require ever more functionality and performance to meet consumer demand. These challenges become more critical and complex when resistive losses in PCB and package structures are significant since resistive losses are temperature dependent. In this webinar, we will look at an electrothermal co-simulation solution for the full hierarchy of electronic systems… CadenceTECHTALK: System-Level Thermal Signoff from Chips Through to Racks
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The need for faster and more efficient Ethernet solutions has never been greater, as the demands of high-performance computing and the rise of big data continue to grow. Join us as we explore the main challenges faced in scaling Ethernet to 1.6T and how the high-performance computing is changing the Ethernet landscape. In this webinar,… The Path to 1.6TbE with 224G Ethernet PHY IP |
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IEEE International Symposium on Hardware Oriented Security and Trust (HOST) is the premier symposium that facilitates the rapid growth of hardware-based security research and development. Since 2008, HOST has served as the globally recognized event for researchers and practitioners to advance knowledge and technologies related to hardware security and assurance. Rapid proliferation of computing and communication… IEEE International Symposium on Hardware Oriented Security and Trust (HOST) |
3 events,
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IC package design teams and characterization teams have had a “throw-it-over-the-wall” relationship for decades, which often delays design releases by months. However, as signal integrity (SI) and power integrity (PI) challenges evolve with multi-die heterogeneous integration, the need to perform SI/PI analysis as part of the design flow has become a requirement to meet compressed… Design Robust IC Packages Faster Using In-Design SI/PI Analysis
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Shine Chung Chairman Attopsemi Technology Revolutionary Metal I-fuse® OTP in FinFET Tech Umesh Sisodia CEO CircuitSutra Transforming Semiconductor Design Using SystemC Based Shift-left ESL Methodologies Roger Espasa CEO & FounderSemidynamics RISC-V, Out-of-Order IP Core, Vector Unit Siddharth Ravikumar Technical Product Manager, Solido IP ValidationSiemens EDA IP, QA, Validation, analog, digital, mixed-signal Michael Seaholm Product Manager… SemIsrael Tech Webinar |
2 events,
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Join us and learn about: TSMC's smartphone, HPC, IoT, and automotive platform solutions TSMC's advanced technology progress on 5nm, 4nm, 3nm, 2nm processes and beyond TSMC's specialty technology breakthroughs on ultra-low power, RF, embedded memory, power management, sensor technologies, and more TSMC 3DFabric™ advanced packaging technology advancement on InFO, CoWoS®, and SoIC TSMC's manufacturing excellence,… TSMC – Austin Technology Workshop |
2 events,
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Presenter: Espen Tallaksen, CEO of EmLogic Abstract Part 1: Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series we will present a step-by-step approach on how to architect a testbench - progressing from basic to advanced techniques. We will first use… Basic Testbench for a Simple DUT |
1 event,
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The Austin RISC-V Group is back, and we're planning a regular schedule of the second Tuesday of every month. This will be an on-line event. We'll be the RISC-V Bivy virtual meeting system, and this is the same as the event on the RISC-V Community site. The use of a microphone and/or camera are not… May 2023 Austin RISC-V Meetup |
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