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IEEE International Symposium on Hardware Oriented Security and Trust (HOST) is the premier symposium that facilitates the rapid growth of hardware-based security research and development. Since 2008, HOST has served as the globally recognized event for researchers and practitioners to advance knowledge and technologies related to hardware security and assurance. Rapid proliferation of computing and communication… IEEE International Symposium on Hardware Oriented Security and Trust (HOST) |
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IC package design teams and characterization teams have had a “throw-it-over-the-wall” relationship for decades, which often delays design releases by months. However, as signal integrity (SI) and power integrity (PI) challenges evolve with multi-die heterogeneous integration, the need to perform SI/PI analysis as part of the design flow has become a requirement to meet compressed… Design Robust IC Packages Faster Using In-Design SI/PI Analysis
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Shine Chung Chairman Attopsemi Technology Revolutionary Metal I-fuse® OTP in FinFET Tech Umesh Sisodia CEO CircuitSutra Transforming Semiconductor Design Using SystemC Based Shift-left ESL Methodologies Roger Espasa CEO & FounderSemidynamics RISC-V, Out-of-Order IP Core, Vector Unit Siddharth Ravikumar Technical Product Manager, Solido IP ValidationSiemens EDA IP, QA, Validation, analog, digital, mixed-signal Michael Seaholm Product Manager… SemIsrael Tech Webinar |
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Join us and learn about: TSMC's smartphone, HPC, IoT, and automotive platform solutions TSMC's advanced technology progress on 5nm, 4nm, 3nm, 2nm processes and beyond TSMC's specialty technology breakthroughs on ultra-low power, RF, embedded memory, power management, sensor technologies, and more TSMC 3DFabric™ advanced packaging technology advancement on InFO, CoWoS®, and SoIC TSMC's manufacturing excellence,… TSMC – Austin Technology Workshop |
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Presenter: Espen Tallaksen, CEO of EmLogic Abstract Part 1: Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series we will present a step-by-step approach on how to architect a testbench - progressing from basic to advanced techniques. We will first use… Basic Testbench for a Simple DUT |
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The Austin RISC-V Group is back, and we're planning a regular schedule of the second Tuesday of every month. This will be an on-line event. We'll be the RISC-V Bivy virtual meeting system, and this is the same as the event on the RISC-V Community site. The use of a microphone and/or camera are not… May 2023 Austin RISC-V Meetup |
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The IEEE Symposium on Field-Programmable Custom Computing Machines is the original and premier forum for presenting and discussing new research related to computing that exploits the unique features and capabilities of FPGAs and other reconfigurable hardware. Over the past two decades, FCCM has been the place to present papers on architectures, tools, and programming models… The 31st IEEE International Symposium On Field-Programmable Custom Computing Machines 
The major annual event of the Israeli semiconductor industry ChipEx2023, the largest annual event of the Israeli semiconductor industry, will be held on May 9, 2023 in Tel Aviv, Israel. ChipEx2023 showcases companies including manufacturers, developers and suppliers of advanced hardware technologies & services. It also includes a technical seminar where the world's leading experts address the industry's most relevant… ChipEx 2023 
Theme Artificial Intelligence, Machine Learning, and Deep Learning: Tactical and Strategic Impacts to Microelectronics Design and Test About MDTS 2023 The IEEE Microelectronics Design & Test Symposium (MDTS) provides a forum for academic and industry researchers and engineers to discuss the latest advances in microelectronics, share their visions in modern microelectronic technologies, and foster academic-industry… The 32nd Microelectronics Design and Test Symposium (MDTS 2023) |
6 events,
Co-located with ACM International Conference on Computing Frontiers 2020 May 9 - May 11, 2023 - Bologna, Italy We are excited to announce a new workshop on the topic of open-source hardware, to be held concurrently with Computing Frontiers 2023. Aim and Scope The workshop aims to bring together researchers and practitioners working in the fields… Workshop on Open-Source Hardware, CF23-OSHW 
VOICE is a developer conference, created by test engineers for test engineers. Each year, the VOICE Developer Conference unites semiconductor test professionals representing the world's leading integrated device manufacturers (IDMs), foundries, fabless semiconductor companies and outsourced semiconductor assembly and test (OSAT) providers to exchange information about the latest technology advancements, express new ideas, share best… Advantest VOICE
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Join us and learn about: TSMC's smartphone, HPC, IoT, and automotive platform solutions TSMC's advanced technology progress on 5nm, 4nm, 3nm, 2nm processes and beyond TSMC's specialty technology breakthroughs on ultra-low power, RF, embedded memory, power management, sensor technologies, and more TSMC 3DFabric™ advanced packaging technology advancement on InFO, CoWoS®, and SoIC TSMC's manufacturing excellence,… TSMC – Boston Technology Workshop |
5 events,
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Wireless devices are ubiquitous, all requiring RF ICs to transmit and receive radio waves via antennas. The radio range can be a few meters for applications such as Bluetooth and WiFi to many kilometers for long range 5G, satellite and radar applications. Today's total RF market is growing rapidly with global RF IC sales exceeding… Synopsys RF / mmWave IC Design Reference Flow with TSMC N6RF and N16FFC Process Nodes |
4 events,
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U2U is your opportunity to learn, grow and connect with fellow technical experts who design leading-edge products using Siemens EDA tools. U2U is focused on these areas: Design For Test & Embedded Analytics Electronic System Design/PCB Design analysis and manufacturing Functional Design & Verification Hardware Assisted Verification High Level Synthesis: Digital design in C++/SystemC IC… User2User Europe 2023
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The programming interfaces of logic simulators are largely the domain of specialists writing proprietary tools and extensions and are only vaguely in the consciousness of many design and verification engineers, if aware at all. Yet the simplest use of such interfaces opens up a whole world of possibilities in extending what is achievable in verifying… The Power of SystemVerilog’s DPI |
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4 events,
Imec’s flagship event on semiconductor advances & deep-tech solutions formerly known as Future Summits. Semiconductors have become increasingly instrumental – and often even dominant – for the future of industries and application domains worldwide. For many decades, imec has played a major role in the global semiconductor industry. Our expertise and partnerships now also progress… ITF World 2023 
We are pleased to invite you to the MunEDA Users Group Meeting 2023. MUGM 2023 will take place on May 16th & 17th (Tue/Wed), 2023 in Munich, Germany. The goal of the event is an intensive exchange of knowledge by new and experienced industrial users. MUGM provides an open forum for engineers interested in MunEDA solutions… MunEDA User Group 2023
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With design boundaries constantly stretched and redefined, traditional borders for “custom design” no longer hold. Creative and intelligent solutions are imperative for boosting overall design, simulation, layout, and verification productivity through ever-changing specifications. Join us for this full-day in-person seminar to learn how Cadence is leveraging its expertise to revolutionize custom design on all fronts… Experience the Future of Custom Design with Virtuoso Studio
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Join us at this webinar to learn more about the Cadence® EMX® Designer, our newly introduced passive component synthesis and optimization solution. In split seconds, the EMX Designer generates very flexible DRC-clean parametric cells of passive devices, such as inductors, transformers, and T-coils. Leveraging the EMX Planar 3D Solver, the industry’s gold-standard electromagnetic modeling engine,… Passive Component Synthesis and Optimization for IC Designs |
3 events,
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Join us on May 17 for the latest 3D-IC webinar series, “Power Integrity Challenges and Solutions for Interposer Design.” The discussion will focus on interposer power analysis as an isolated case and in context with the dice instantiated in a 3D-IC device. The presentation will then explore the completed multi-chip design in a system simulation.… Power Integrity Issues and Solutions for Silicon Interposers |
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When employing process simulation to generate a complex device structure, TCAD engineers often face the task of reproducing the exact etch profile that has been observed in semiconductor fabrication. Silvaco Victory Process offers several geometric models to efficiently achieve etch geometries that accurately match microscopy images (e.g., transmission electron microscopy). In this webinar, we present… Learn How to Use Victory Process TCAD Geometric Etch Models in FinFET and Memory Applications
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Mark your calendar to join us on Thursday, May 18 at 11 a.m. EDT for an Open Compute Project (OCP) Foundation educational webinar on Addressing Silent Data Errors for Resilient Data Centers. During the webinar, you will learn: What is the magnitude of silent data errors (SDE) How does SDE impact end users What is… Addressing Silent Data Errors for Resilient Data Centers
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The evening begins at the Keysight office, Thursday, May 18, at 5:00pm with the ESD Alliance Annual Membership Meeting. You'll get an overview of the past year's activities and discover what's in store for 2023. The meeting flows directly into a Welcome Reception followed by the powerful CEO Outlook. Enjoy a lively, nourishing networking reception that kicks off the CEO Outlook… Annual ESDA Membership Meeting & CEO Outlook |
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The IEEE International Symposium on Circuits and Systems (ISCAS) is the flagship conference of the IEEE Circuits and Systems (CAS) Society and the world’s premiere forum for researchers in the active fields of theory, design and implementation of circuits and systems. Keynote Speakers Dr. Margaret Martonosi Margaret Martonosi is the US National Science Foundation’s (NSF)… ISCAS 2023 |
2 events,
The Summit attracts a global audience of technology professionals from companies developing computer vision and edge AI-enabled products including embedded systems, cloud solutions and mobile applications. Why attend? It's a First-Rate Program with Powerful Insights into Practical Perceptual AI. Join us for four days of learning—from tutorials to deep-dive days, covering the latest technical insights,… Embedded Vision Summit 2023 |
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7 events,
Wednesday, May 24, 2023 and Thursday, May 25, 2023 The industry is moving to multi-die systems to benefit from the greater compute performance, increased functionality, and new levels of flexibility. Challenges for multi-die systems are exacerbated and require greater focus on a number of requirements such as early partitioning and thermal planning, die/package co-design, secure… Requirements for Multi-Die System Success
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Case Studies in Low-Power Smart Vision and Post-Quantum Cryptography Applications The slow-down of Moore’s law and Dennard scaling triggered an increased awareness for application-specific instruction-set processors (ASIPs). These processors implement a specialized instruction-set architecture (ISA) tailored to the application domain, often starting from a baseline such as the RISC-V ISA. ASIPs can replace traditional fixed-function… Extending RISC Processors into Flexible Accelerators using ASIP Designer
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Want to learn how Tier One suppliers are using network modeling and simulation in the design and optimization of network topology and gateway architecture. Then attend this Webinar by DENSO. Efficient in-vehicle network development through simulation combining network and ECU hardware and software elements Time Zone: Japan - 3:00 PM (In Japanese) Asia - 3:00… DENSO discusses Verification of network relay performance using VisualSim
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In this event, experts from Martin-Luther-Universitat Halle Wittenberg, University of York, and Synopsys QuantumATK will present how to use ab initio DFT modeling and atomistic spin dynamics simulations of MTJs to guide and accelerate the technological development of magnetic memory such as STT and SOT-MRAM. Investigating the potential of novel magnetic tunnel junction (MTJ) materials… Advancing MRAM Technology with Atomistic Spin Dynamics Simulations |
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Synopsys Webinar | Thursday, May 25, 2023 | 9:00 a.m. PT According to a recent Semico Research report, the RISC-V Core IP market is expected to grow at a 34.9% CAGR through year 2027. With increasing popularity, it is of utmost importance that the RISC-V Core IPs are secure and bug free. In this… Don’t Take the Risk, Formally Verify Your RISC-V Cores |
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IP vendor SiFive has been at the forefront of RISC-V’s rapidly growing adoption across a wide array of markets and applications. In this joint presentation with Ansys, SiFive will describe how achieving maximum compute density - compute horsepower per mm2 and per mW (e.g SPECint2006/mm2) - has been a driving goal for SiFive’s portfolio of… SiFive Maximizes Compute Density With Its RISC-V Processor Cores
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STAC Summits bring together CTOs and other industry leaders responsible for solution architecture, infrastructure engineering, application development, machine learning/deep learning engineering, data engineering, and operational intelligence to discuss important technical challenges in trading and investment. |
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Abstract: Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series, we will present a step-by-step approach on how to architect a testbench - progressing from basic to advanced techniques. We will first use a simple DUT then go to a more… Advanced Testbench for a Simple DUT
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Increasingly complex automotive systems are driving the need for new and powerful E/E architectures, and new technology is emerging that offers a significant computational increase compared to previous generation SoCs. To deliver next-generation, differentiated software solutions, model-based design (MBD) workflows must be deployed to handle this new level of complexity. Code generation solutions that optimize… Accelerate Software Innovation Through Target-Optimized Code Generation and Virtual Prototypes |
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