Calendar of Events
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This packed conference brings together industry engineers, researchers and top experts involved in advanced packaging and microelectronics assembly. IMAPS Symposium offers a robust technical program with 5 concurrent tracks and 100+ speakers and posters covering SiP Design / Manufacturing Optimization; Wafer Level / Panel Level (Advanced RDL); High Performance, High Reliability; Advanced Packages (Flip Chip, 2.5D,… 56th International Microelectronics Assembly and Packaging Society (IMAPS) |
3 events,
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Learn About: Emerging advanced node design challenges and corresponding design flows and methodologies for N2, N3/N3E/N3P/N3AE, N4/N4P, N5/N5A, N6/N6e/N6RF/N7, N12e, and N22 Latest updates on TSMC 3DFabric™ chip stacking and advanced packaging processes, InFO, CoWoS®, and SoIC, 3DFabric Alliance, and 3Dblox™ standard, plus innovative 3Dblox-based design enablement technologies and solutions, targeting HPC, AI/ML, and mobile… TSMC 2023 Europe OIP Ecosystem Forum
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Verisium Debug offers comprehensive debugging capabilities. From RTL and UVM testbench to UPF low-power designs, Cadence’s unified debugging platform helps users debug. In this webinar, users will learn about the available features in Verisium Debug for UVM testbench and use these unique capabilities to visualize and debug the UVM testbench. What you will learn Understand… Verisium Debug for UVM Testbench |
3 events,
EDPS 2023 is approaching fast! The program is firming up - please see the program page for a preliminary list of talks. REGISTRATION IS NOW OPEN. Everyone, including speakers, must register. 2023-ieee-edps.eventbrite.com Note that this year we'll be meeting on the Synopsys Campus. Synopsys Building 1 800 North Mary Avenue Sunnyvale, CA, 94085 Most of the talks… EDPS 2023
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Abstract As FPGA technology continues to evolve - to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area - design verification becomes increasingly challenging. Lab-based FPGA testing and bring-up alone are clearly insufficient, especially for safety-critical designs, and FPGA teams are adopting advanced design verification… FPGA Design Verification – Advanced Methods |
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International Test Conference, the cornerstone of TestWeek™ events, is the world’s premier conference dedicated to the electronic test of devices, boards and systems-covering the complete cycle from design verification, test, diagnosis, failure analysis and back to process and design improvement. At ITC, test and design professionals can confront the challenges the industry faces, and learn how… International Test Conference 2023 |
1 event,
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4 events,
CadenceLIVE Europe 2023 – experience the power of intelligent system design - brings together users, developers, and industry experts to network, share ideas, and inspire design innovation in the most complex electronics and intelligent systems. The event features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products. Attendees will be able to… CadenceLIVE Europe 2023
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Join us for a day filled with insights, innovation, and networking in the semiconductor industry. The verification landscape is evolving, and we're here to help you navigate it. At this symposium, we’ll be going through some of the most challenging use cases in chip design today, while exploring best practices and the latest innovations for… Synopsys Verification Technical Symposium 2023 – Israel
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Shift Left to Raise Design Productivity We're ready to demo the latest release of our suite of electronic design automation (EDA) software tools so that you can learn how to increase productivity by shifting left your design process and product development cycles. Four Tracks to Choose from We'll kick off each session with an overview… Keysight EDA 2024 |
3 events,
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In this Webinar, we will focus on the performance-power-area trade-off in implementing signal processing algorithms on Xilinx FPGA by partitioning the tasks of the algorithms onto the processors, logic and AI Engines resident in the AMD-Xilinx Versal FPGA. Key Takeaways: Discover the inner workings of FPGA components: Processor, Logic Elements, AIE/Tensor, and more. Understand latency… Mapping signal processing algorithms on AMD-Xilinx Versal to meet timing and power constraints |
4 events,
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Synopsys is hosting a Technical Symposium focusing on critical aspects of doing state of the art designs at established and emerging nodes. This event provides an opportunity for users to stay connected with the latest innovations as well as getting tips & tricks and best practices that fellow users and Synopsys experts will share. Multiple… Synopsys Technology Symposium UK 2023
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The heterogeneous integration of chips and chiplets in IC packages is all the rage as we face “More than Moore” performance challenges. While these innovative design practices successfully address performance goals, some design teams find that IC packages may overheat if they do not carefully plan for heat dissipation. This webinar will show how design… Proactively Address Thermal Concerns in Advanced IC Packages
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Presenter: Dr. Debendra Das Sharma, UCIe Consortium Chairman and Intel Senior Fellow, Chief Architect of I/O Technology and Standards at Intel The UCIe™ (Universal Chiplet Interconnect Express™) 1.1 Specification was released in August 2023, delivering valuable improvements to the chiplet ecosystem, extending reliability mechanisms to more protocols and supporting broader usage models. This webinar will provide… The UCIe™ 1.1 Specification: Future Applications of Chiplets |
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1 event,
With the test technology facing its grand challenges to ensure the quality of ICs and electronic systems, incorporating more and more sophisticated manufacturing processes and system integration technologies in various emerging applications such as Internet of Things, cloud computing, automotive electronics, etc., global proliferation and cooperation is increasingly more important. The Asian Test Symposium (ATS)… IEEE 32nd Asian Test Symposium |
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EPEPS is the premier international conference on advanced and emerging issues in electrical modeling, analysis and design of electronic interconnections, packages and systems. It also focuses on new methodologies and design techniques for evaluating and ensuring signal, power and thermal integrity in high-speed designs. EPEPS is jointly sponsored by the IEEE Electronics Packaging Society, IEEE Microwave… EPEPS 2023 |
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4 events,
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This is to inform you that the next DVClub Europe meeting takes place on Tuesday 17th October with a theme of "AI/ML in Verification". This DVClub consider how we can save time and effort whilst improving time-to-market through the application of AI/ML to verification. Agenda (BST) 12:00 Welcome and Introduction - Mike Bartley, Senior Vice President -… DVClub Europe – AI/ML in Verification
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Welcoming Remarks Seishu Arai VP, Head of Japan Office, Samsung Electronics Samsung Keynote Siyoung Choi President and GM, Foundry Business, Samsung Electronics Guest Speech I Junichiro Makino Professor, Kobe University Guest Speech II Sumiko Kanamori Automotive HPC, Analog & Power Solutions Gr. Digital Head of H/W Unit, VP, Renesas Electronics Corporation Guest Speech III Kazuoki… Samsung Foundry Forum 2023 Tokyo, Japan |
5 events,
Ready to share and discuss the latest design and verification best practices with your peers from around the world? It’s time for our annual CadenceCONNECT: Jasper™ User Group Conference, held on October 18 and 19 at the Cadence San Jose campus. This interactive, in-depth technical conference connects designers, verification engineers, and engineering managers from around… Jasper User Group 2023
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Event Overview Date: Wednesday, October 18, 2023 Time: 8:30am – 4:00pm, followed by an exclusive networking event Location: Brazos Hall, Austin, TX There is an unprecedented demand for advanced-node chip design that pushes beyond traditional boundaries. Computing power, security, reliability, and other multifaceted requirements have surpassed the basic performance, power consumption, and area constraints of traditional chip design. The… The Race is On!
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Date: Wednesday, October 18, 2023 Time: 8:30am PT | 10:30am CT | 11:30am ET Join us for this 45-minute webinar to learn how the Cadence-managed, EDA-optimized, ready-to-use, and secure ISO-certified cloud platform delivers a fully integrated and proven environment to jump-start product design, verification, and implementation. See the platform in action as we demo the productivity features… Soar to New Heights of Productivity using Cadence Managed Cloud Services
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Today’s modern electronic designs require ever more functionality and performance to meet consumer demand. These challenges become more critical and complex when resistive losses in PCB and package structures are significant since resistive losses are temperature dependent. In this webinar, we will look at an electrothermal co-simulation solution for the full hierarchy of electronic systems… System-Level Thermal Signoff from Chips Through to Racks |
3 events,
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We're inviting global partners and customers to our upcoming Samsung Foundry Forum (SFF) and Samsung Advanced Foundry Ecosystem (SAFE™) Forum 2023. The events will provide opportunities to share insights and innovative technologies to build a strong foundry ecosystem to accelerate innovation beyond boundaries. Join us to experience the spirit and power of innovation. SFF &… Samsung Foundry Forum 2023 EMEA
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When designing any new system, safety and reliability are key factors in determining if a system is safe for real-world deployment and if there are sufficient contingency plans for worst case scenarios. This is no different for the designs targeted for FPGAs based deployments. Today, FPGA based designs are utilized in many safety critical systems in the… High Reliability and Functional Safety Applications for FPGA |
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SemIsrael Expo 2023 is the premier professional semiconductor event in Israel. The event brings together hundreds of Israeli semiconductor professionals from all fields and aspects of the semiconductor industry. The Expo will host some 750 semiconductor professionals from all the Israeli semiconductor community; local fabless & startups, local R&D offices of multinationals and IDMs, foundries,… SemIsrael Expo 2023 |
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Silvaco UseRs Global Events (SURGE) bring together users, developers, and industry experts of the EDA, IP, and TCAD communities to understand new semiconductor technologies, innovative applications, and techniques for realizing advanced designs. Presentations A variety of presentations will cover semiconductor device simulation, circuit design and verification, and IP design. Roadmaps and exciting technology updates will… Silvaco UseRs Global Event (SURGE) 2023 – USA |
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Jointly sponsored by IEEE and ACM, ICCAD is the premier forum to explore new challenges, present leading-edge innovative solutions, and identify emerging technologies in the electronic design automation research areas. ICCAD covers the full range of CAD topics – from device and circuit level up through system level, as well as post-CMOS design. ICCAD has… ICCAD 2023 |
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3 events,
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STAC Summits bring together CTOs and other industry leaders responsible for solution architecture, infrastructure engineering, application development, machine learning/deep learning engineering, data engineering, and operational intelligence to discuss important technical challenges in trading and investment. WHEN Tuesday, October 31, 2023 STAC Exchange (Exhibits) opens at 8:30am CDT Conference starts at 9:00am CDT Networking lunch at… STAC Summit
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The comprehensive verification of analog mixed-signal (AMS) designs has challenges in schedules and implementations due to the vast divergence in design flows of the analog and digital portions of the SoC. These discrepancies include priorities in simulation cycles (accuracy versus performance), design methodologies, and verification of functionality. Over multiple decades, design verification (DV) has evolved… Enhance Verification Quality with the Xcelium Mixed-Signal App |
3 events,
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Join us on Wednesday, November 1st, for an eye-opening exploration of the inadequacy of common design data and IP management capabilities in the face of today’s intricate semiconductor chip designs. Discover the keys to unlocking unparalleled success in your upcoming designs through cutting-edge capabilities and strategies that are reshaping the industry. Don’t miss this exclusive opportunity… Mastering the Art of Managing IP, Chiplets, and Design Data
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Are you ready to lead the way in gate-level digital simulations (GLS)? Dive into Cadence’s exclusive webinar and uncover the revolutionary Xcelium Multi-Core (MC) App—a game changer for GLS, allowing you to parallelize and expedite simulations like never before. What You'll Gain: Insight: Understand why the Xcelium MC App is crucial for DV engineers looking… Warp Speed Gate-Level Simulations with the Xcelium Multi-Core App |
3 events,
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Join us for "RISC-V in... Space" on November 2, 2023, as we explore the exciting intersection of RISC-V, electronics design, and space! Agenda 9:30 AM - 10:00 AM Registration & Welcome 10:00 AM - 12:00 PM Case Study Presentations: Tenstorrent, Synopsys, RISC AI, Arteris IP 12:00 PM - 1:00 PM Lunch Buffet 1:00 PM - 3:00 PM Case Study Presentations: Breker Systems, Imperas,… RISC-V in Space
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Power integrity (PI) is a major challenge for chip designers in the era of ubiquitous data, hyperconnectivity, and AI. Design size is exploding, and innovations in heterogenous integration are adding to PI complexity. These changes and challenges are ushering in the IR2.0 era ― a new paradigm for power integrity design and analysis. As a… IR 2.0 – Building a New Paradigm for Power Integrity Design and Analysis |
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