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PCIe

How Synopsys Interface IP and Arm Interoperate to Accelerate System IO and Memory Performance

In this webinar, Synopsys and Arm describe how their recent collaboration helps maximize system performance and shorten Arm-based SoC design cycles. Learn how to minimize HPC/data center SoC design risk and ensure end-to-end IP integration, using available Arm reference designs and interoperability reports. Find out how Synopsys’ interface IP for the most widely used protocols… Read More »How Synopsys Interface IP and Arm Interoperate to Accelerate System IO and Memory Performance

Defending the Cloud: PCIe and CXL Data Security for High-Performance Computing

Cloud computing is going through a significant overhaul and continues to grow globally with increasing presence of hyperscale cloud providers for big data, high-performance computing (HPC), and analytics. In-house data centers are increasingly going off-premise, resulting in the co-location of data centers that manage and store data for companies and application developers to improve scalability… Read More »Defending the Cloud: PCIe and CXL Data Security for High-Performance Computing

CXL and IDE: Important Considerations of Protecting High Speed Interconnects

In a few short years, CXL (Compute Express Link) has evolved from an idea to a rapidly proliferating low latency interconnect standard being adopted into data centers, high performance computing, and cloud computing. However, as the adoption has increased, so has the security threat model users face. To address this, the CXL 2.0 standard has… Read More »CXL and IDE: Important Considerations of Protecting High Speed Interconnects

PCIe 6.0 From IP to Interconnect in High-Performance Computing

ABSTRACT: PCI Express (PCIe) is one of the most popular interface technologies in the world. Interconnects for high-performance computing (HPC) in the data center, cloud and AI edge continue to increase in speed and density. System architects, SoC designers, PCB developers and SI engineers are challenged as never before to implement bleeding edge solutions. In… Read More »PCIe 6.0 From IP to Interconnect in High-Performance Computing

Verification of PCIe-based FPGA Designs Requiring DO-254 Compliance (US)

PCIe-based FPGA designs are becoming popular within avionics systems. However, the verification of such designs for DO-254 compliance with design assurance level (DAL) A or B is problematic. FPGA designs that use asynchronous clocks with multiple high-speed serial interfaces such as PCIe produce non-deterministic results during physical tests. Simulation results are optimized because they are… Read More »Verification of PCIe-based FPGA Designs Requiring DO-254 Compliance (US)

Overcoming PCIe 6.0 System Integration and Pre-Silicon Validation Challenges

PCIe, the most popular interconnect in compute, AI and storage systems, is now offering faster data rate, higher performance, lower power and lower latency than the previous generation. Because of these reasons and the addition of PAM-4 signaling, challenges such as signal integrity, power integrity, implementation, IP integration and more must be considered when designing… Read More »Overcoming PCIe 6.0 System Integration and Pre-Silicon Validation Challenges

Evaluating UCIe based multi-die architectures to meet timing and power constraints

Multi-die architectures have evolved from proprietary to industry standard UCIe.  UCIe can accommodate the bulk of designs today from 8 Gbps per pin to 32 Gbps per pin for high-bandwidth applications from networking to Hyperscale data centers. To help your UCIe adoption journey, we present VisualSim Architect and the associated UCIe/PCIe6.0 IPs to explore and… Read More »Evaluating UCIe based multi-die architectures to meet timing and power constraints

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