Abstract As FPGA technology continues to evolve – to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area – design verification becomes increasingly challenging. Lab-based… FPGA Design Verification – Advanced Testbench Implementation
As FPGA technology continues to evolve – to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area – design verification becomes increasingly challenging. Lab-based FPGA… FPGA Design Verification – Planning
Abstract: Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series, we will present a step-by-step approach on how to architect a… Advanced Testbench for a Complex DUT
Abstract: Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series, we will present a step-by-step approach on how to architect a… Advanced Testbench for a Simple DUT
Presenter: Espen Tallaksen, CEO of EmLogic Abstract Part 1: Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series we will present… Basic Testbench for a Simple DUT
The programming interfaces of logic simulators are largely the domain of specialists writing proprietary tools and extensions and are only vaguely in the consciousness of many design and verification engineers, if aware at all. Yet… The Power of VHDL’s VHPI
A logic simulator’s programming interfaces can be used for not only verifying logic IP but also the co-development of logic and embedded software. Our ‘Introducing Logic Simulator Programming Interfaces for FPGA designs’ three-part webinar series… The Power of Verilog’s PLI and VPI for FPGA Designs
The use of advanced verification tools can significantly reduce the number of non-trivial bugs, save engineering time and resources and, more importantly, increase the reliability of FPGA designs. Static design verification is an essential part… Linting and Clock Domain Crossing Analysis for Microchip FPGA Designs
The embedded world Exhibition&Conference provides a global platform and a place to meet for the entire embedded community, including leading experts, key players and industry associations. It offers unprecedented insight into the world of embedded… Embedded World
Writing code is easy. Reading code is hard. Maintaining code is hard. Writing “good” code is hard. So what’s “good code”? Don’t despair: the software engineering community has come up with tons of practical solutions!… Engineering best practices for Python-based testbenches with cocotb