As the automotive market moves toward electrified drivetrains and autonomous driving systems, chip makers increasingly need to design integrated mixed-signal chips that meet the ISO 26262 automotive certification. With these complex designs, designers will require… Analog Fault Injection Simplifies ISO 26262 Compliance
Analog and mixed-signal verification has always been a challenge for design and verification engineers. It has become tedious with the increasing complexity of SoC designs. Because the analog behavior of key design blocks cannot be… Mixed-Signal SoC Verification Simplified with Xcelium Simulator
SemIsrael Expo is the premier professional semiconductor event in Israel. The event brings together hundreds of Israeli semiconductor professionals from all fields and aspects of the semiconductor industry. The Expo will host some 750 semiconductor… SemIsrael Tech Webinar
In the semiconductor foundry business we all know that TSMC sits at the top, followed by: Samsung, UMC, GlobalFoundries and SMIC. So Intel wants back into this service business, and is slowly rebuilding its capabilities… Intel Foundry Services, It’s Awakening
Electronic products with 3D-ICs face growing system challenges related to signal, power, and thermal integrity. Design density can lead to performance issues caused by heat, crosstalk, and power noise. In this session, we will address… CadenceTECHTALK: Overcoming System-Level 3D-IC Electrical and Thermal Challenges
A 3D-IC includes the package, interposer, multiple chiplets, through-silicon vias (TSVs), and through-dielectric vias (TDVs). Supplying power to the chiplets and dissipating heat through these various components poses a major power integrity (PI) and thermal… CadenceTECHTALK: 3D-IC Chip-Centric Power and Thermal Integrity with High-Performance Hierarchical Analysis
System planning is a major part of multi-chiplet design. Whether it’s a 2.5-D configuration with an interposer or full-stacked 3D design mounted on a package, it is important to have an automated way to do… CadenceTECHTALK: System Planning and Implementation for Different 3D-IC Design Styles
Multi-chiplet design and packaging introduces extra design and analysis requirements like system planning, bump alignment, TSV and micro-bump insertion and extraction, electrothermal analysis, cross-die STA, and inter-die physical verification, which must be considered early during… CadenceTECHTALK: Efficient Multi-Chiplet Design with Integrity 3D-IC Unified Platform
Want to take a tour of this powerful power estimation tool and gear up so you understand the Joules flow? Join Cadence Training and Sr Principal Education Application Engineer Neha Joshi for this free technical… Introduction to the Joules RTL Power Solution
