Webinar
Advanced Antenna Design and Integration Through Circuit/EM Co-Simulation
The Cadence® AWR® V16 for RF Design Excellence Webinar Series introduces the latest capabilities in Cadence® AWR Design Environment® Version 16 (V16), providing ready access to Cadence Clarity™ 3D Solver and Celsius™ Thermal Solver for unconstrained capacity to solve large-scale and complex RF systems directly from within the RF design platform. Our next webinar in… Read More »Advanced Antenna Design and Integration Through Circuit/EM Co-Simulation
Python in Verification Online Meetup
Veriest is inviting you to another event in our series of online Verification Meetups. This time, we'll have two presentations on the polemic topic of using Python in Verification, one by an industry expert and the other by one of Veriest technical leaders. Save the date and watch this space for more details!
Compare Performance-power of Arm Cortex vs RISC-V for AI applications
In the Webinar, we will show you how to construct, simulate, analyze, validate, and optimize an architecture model using pre-built components. We will compare micro and application benchmarks on system SoC models containing clusters of ARM Cortex A53/A77/A65AE/N1, SiFive u74, and other vendor cores. Aside from the processor resources such as cache and memory, the… Read More »Compare Performance-power of Arm Cortex vs RISC-V for AI applications
Using OVL for Assertion-based Verification of Verilog and VHDL Designs
Open Verification Library (OVL) is a library of property checkers for digital circuit descriptions written in popular Hardware Description Languages and maintained by Accelera. The OVL checkers could be used not only in dynamic simulation, but also in formal verification and emulation. Also, the OVL-based verification technology provides the easiest way for designers to implement… Read More »Using OVL for Assertion-based Verification of Verilog and VHDL Designs
Managing SoC Subsystems and Other Hierarchy With Methodics IPLM
For the past 10+ years, semiconductor design has moved from a project-based "start again" mindset to a more modular, "IP-centric" approach. This has significantly reduced project cost and improved time-to-market by encouraging the outsourcing of niche areas of the design to specialists, enabling the use of foundry sourced IP (often for free) and emphasizing the… Read More »Managing SoC Subsystems and Other Hierarchy With Methodics IPLM
Xcelium ML for 5X Faster Regression Throughput
Overview Regressions time often becomes one of the biggest challenges to meet the tight project schedule with increasing complexity of the SoC designs and shorter time to market. Verification engineers apply a coverage-driven methodology and run a large number of constrained random tests with multiple seeds in massive regressions to meet their coverage goals. Thus,… Read More »Xcelium ML for 5X Faster Regression Throughput
Intelligent Cross-Platform Workflows for RF PCB Integration
The last webinar in The Cadence® AWR® V16 for RF Design Excellence Webinar Seriesintroduces groundbreaking cross-platform workflows from AWR® software to Allegro® PCB Designer, which help to deliver up to a 50% reduction in turnaround time compared to competing solutions. RF IP integration within a larger mixed-signal PCB system is hampered by disjointed workflows between… Read More »Intelligent Cross-Platform Workflows for RF PCB Integration
Understanding Random Stability in SystemVerilog and UVM
Webinar Overview: A common issue with constrained random simulation is being able to reproduce random stimulus for debug purposes and for locking down regressions test suites. This is especially problematic when the source code needs to be modified and is known in SystemVerilog as random stability. In this webinar, we explain: Random stability in SystemVerilog… Read More »Understanding Random Stability in SystemVerilog and UVM
Constraint Random Verification with Python and Cocotb
Abstract: Testing digital hardware has never been an easy job, and it won’t get easier any time soon. But that doesn’t mean writing test code can’t be enjoyable and productive! Cocotb, an approach to use Python as verification language, is bringing the joy back to verification. It allows developers to start with small, directed testbenches,… Read More »Constraint Random Verification with Python and Cocotb
Boost LPDDR5 Verification from IP to System Level
Overview Low power DRAM is being adopted in a wide array of markets, including automotive, PCs and networking systems built for 5G and AI applications. The specification complexity is increasing to meet higher bandwidth, better performance and extended latencies for multiple use cases. Ensuring that JEDEC low-power double data rate 5 (LPDDR5) specification and overall… Read More »Boost LPDDR5 Verification from IP to System Level
CXL and IDE: Important Considerations of Protecting High Speed Interconnects
In a few short years, CXL (Compute Express Link) has evolved from an idea to a rapidly proliferating low latency interconnect standard being adopted into data centers, high performance computing, and cloud computing. However, as the adoption has increased, so has the security threat model users face. To address this, the CXL 2.0 standard has… Read More »CXL and IDE: Important Considerations of Protecting High Speed Interconnects
Workforce Shortages—Meeting Challenges for the Semiconductor Industry
As demand for semiconductors is increasing, foundries and other makers of chips are expanding their manufacturing capacities. With new fabs bringing thousands of new jobs to the US, Texas is ready to secure many of those positions. Where will we find the talent to fill the upcoming surge of engineering and technical personnel needed to support our… Read More »Workforce Shortages—Meeting Challenges for the Semiconductor Industry