Calendar of Events
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1 event,
Jointly sponsored by IEEE and ACM, ICCAD is the premier forum to explore new challenges, present leading-edge innovative solutions, and identify emerging technologies in the electronic design automation research areas. ICCAD covers the full range of CAD topics – from device and circuit level up through system level, as well as post-CMOS design. ICCAD has… ICCAD 2023 |
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3 events,
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STAC Summits bring together CTOs and other industry leaders responsible for solution architecture, infrastructure engineering, application development, machine learning/deep learning engineering, data engineering, and operational intelligence to discuss important technical challenges in trading and investment. WHEN Tuesday, October 31, 2023 STAC Exchange (Exhibits) opens at 8:30am CDT Conference starts at 9:00am CDT Networking lunch at… STAC Summit
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The comprehensive verification of analog mixed-signal (AMS) designs has challenges in schedules and implementations due to the vast divergence in design flows of the analog and digital portions of the SoC. These discrepancies include priorities in simulation cycles (accuracy versus performance), design methodologies, and verification of functionality. Over multiple decades, design verification (DV) has evolved… Enhance Verification Quality with the Xcelium Mixed-Signal App |
3 events,
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Join us on Wednesday, November 1st, for an eye-opening exploration of the inadequacy of common design data and IP management capabilities in the face of today’s intricate semiconductor chip designs. Discover the keys to unlocking unparalleled success in your upcoming designs through cutting-edge capabilities and strategies that are reshaping the industry. Don’t miss this exclusive opportunity… Mastering the Art of Managing IP, Chiplets, and Design Data
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Are you ready to lead the way in gate-level digital simulations (GLS)? Dive into Cadence’s exclusive webinar and uncover the revolutionary Xcelium Multi-Core (MC) App—a game changer for GLS, allowing you to parallelize and expedite simulations like never before. What You'll Gain: Insight: Understand why the Xcelium MC App is crucial for DV engineers looking… Warp Speed Gate-Level Simulations with the Xcelium Multi-Core App |
3 events,
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Join us for "RISC-V in... Space" on November 2, 2023, as we explore the exciting intersection of RISC-V, electronics design, and space! Agenda 9:30 AM - 10:00 AM Registration & Welcome 10:00 AM - 12:00 PM Case Study Presentations: Tenstorrent, Synopsys, RISC AI, Arteris IP 12:00 PM - 1:00 PM Lunch Buffet 1:00 PM - 3:00 PM Case Study Presentations: Breker Systems, Imperas,… RISC-V in Space
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Power integrity (PI) is a major challenge for chip designers in the era of ubiquitous data, hyperconnectivity, and AI. Design size is exploding, and innovations in heterogenous integration are adding to PI complexity. These changes and challenges are ushering in the IR2.0 era ― a new paradigm for power integrity design and analysis. As a… IR 2.0 – Building a New Paradigm for Power Integrity Design and Analysis |
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2 events,
Each day, thousands of engineers around the world collaborate and contribute to advance RISC-V, the open-standard instruction set architecture that is defining the future of open computing. The RISC-V community shares the technical investment and helps shape the architecture’s strategic future so everyone may create more rapidly, enjoy unprecedented design freedom, and substantially reduce the… RISC-V Summit US
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The RISC-V Instruction Set Architecture (ISA) is the future of computing. As an open standard, RISC-V is accelerating innovation and enabling unprecedented design freedom across every computing application. You've seen the headlines and stories. Now, here's your chance to learn all about RISC-V and why it is being rapidly adopted by organizations of all size… RISC-V 101 |
3 events,
Experience the unprecedented growth opportunities in the semiconductor and electronics industry, fueled by rapid advancements in Artificial Intelligence (AI). Embrace the paradigm shift from software-centric approaches to hardware-centric solutions, captivating emerging markets in the realm of AI. Witness the powerful convergence of breakthrough technologies like the Internet of Things (IoT) and AI, igniting a renaissance… IESA AI Summit
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The DataCenter Insight Platform is an enterprise software solution that simplifies data center capacity management by making it proactive, rather than reactive. The platform is a database of data center “digital twins”—virtual models reflecting the aggregate of an organization’s toolsets and add/move/change workflows. By bringing together data that is typically siloed and using predictive computational… Proactive Data Center Management with Insight Platform |
5 events,
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Learn About: Emerging advanced node design challenges and corresponding design flows and methodologies for N2, N3/N3E/N3P/N3AE, N4/N4P, N5/N5A, N6/N6e/N6RF/N7, N12e, and N22 Latest updates on TSMC 3DFabric™ chip stacking and advanced packaging processes, InFO, CoWoS®, and SoIC, 3DFabric Alliance, and 3Dblox™ standard, plus innovative 3Dblox-based design enablement technologies and solutions, targeting HPC, AI/ML, and mobile… TSMC 2023 Taiwan OIP Ecosystem Forum
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This webinar focuses on three specific aspects of the UVM register layer that will help you to model in UVM some of the less obvious ways in which registers can behave, such as non-linear addressing, burst access mode, registers accessed through an embedded CPU, and quirky registers. It will cover the following topics: Using user-defined… Deep Dive into the UVM Register Layer: User-Defined Doors, Predictors, and Callbacks
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Synopsys Webinar – Part I In this 3-part Synopsys webinar series, we will present how hyperscale data centers are going through a paradigm shift with the advent of technologies like Artificial Intelligence (AI) and edge compute requiring hyperscale data centers to support exponential growth of data volume. This volume of network traffic demands an increase… CMOS Circuit Techniques for Wireline Transmitters Part I |
4 events,
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IP share and reuse is fundamental for efficient chip design. But in order to do this efficiently we need tools and methods. On the software side, the concept of package managers is widely used to build a product from many different sources, but chip designers often rely on ad-hoc solutions which tends to build up… CHIPS Alliance – FuseSOC: Package manager and build abstraction tool for FPGA/ASIC development
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cocotb enables Python-based hardware verification, and it integrates into your simulator of choice, such as Aldec's Riviera-PRO and executes Python testbenches in that context. In this webinar, we will look at ways to invoke your simulator of choice in a way that also starts with cocotb. We will show ways to extend the setup to… Ways to run cocotb: makefiles, cocotb-test, or your custom setup
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Electronics design engineering teams are under incredible pressure to quickly deliver innovative new product designs to meet skyrocketing market demand. Sign up for this webinar to learn more about designing better consumer electronics products thanks to simulation in the cloud. About this Webinar Consumer electronic devices are part of our daily lives and include phones,… Elevating Consumer Electronics Design Through Cloud-Based Simulation |
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1 event,
Saving global resources by increasing energy efficiency is among the most significant problems that global society must address today. To achieve this, a major target is developing efficient and reliable power electronics devices for providing the required high-performing hardware components. Power semiconductors based on silicon carbide (SiC) and gallium nitride (GaN) technologies are becoming increasingly… ISTFA 2023 |
2 events,
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Event Overview Date: Monday, November 13, 2023 Time: 8:30am – 4:00pm, followed by an exclusive networking event Location: Cadence Headquarters, San Jose, CA There is an unprecedented demand for advanced-node chip design that pushes beyond traditional boundaries. Computing power, security, reliability, and other multifaceted requirements have surpassed the basic performance, power consumption, and area constraints of traditional chip design.… CadenceCONNECT: The Race Is On! |
6 events,
The Design and Verification Conference & Exhibition Europe (DVCon Europe) is the premier European technical conference on system, software, design, verification, validation and integration. It is a place where the latest methodologies and technologies of tools, languages, and standards for integrated and embedded systems and products are shared and discussed. Applications of interest include (but… DVCon Europe 2023
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re you harnessing the full power of your PCB design software? In this live discussion, experts Stephen Chavez and Ray Macias will discuss the benefits of using PCB design automation, and show how certain capabilities such as component placement, trace routing, and generating manufacturing outputs to include intelligent data formats can improve your design cycle times. They’ll offer… PCB Design Best Practices: Design Automation
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IP cores require integration into top-level subsystems and/or SoCs. Writing constraints manually for top level design is prone to errors and difficult to verify and manage. This Synopsys webinar will cover how automated SDC constraints promotion from the IP to SoC level provides high-quality SDC using Synopsys Timing Constraints Manager relative to manual time-consuming approaches. We will… Automated Constraints Promotion Methodology from IP to SoC for Complex Designs
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As semiconductor industry leaders, Bosch, Infineon, Nordic Semiconductor, NXP, and Qualcomm collaborate to drive the acceleration of automotive RISC-V semiconductors, join us for an insightful webinar on how you too can unlock the full potential of RISC-V within your automotive SoC. Featuring Andes Technology and Green Hills Software, this webinar will offer key insights into… Leverage Certified RISC-V IP to Craft ASIL ISO 26262 Grade Automotive Chips |
7 events,
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I would like to invite you to attend our upcoming webinar on Wednesday, November 15 at 8 a.m. PST. This 1-hour panel will feature SoC experts from CARIAD, Infineon, NXP and proteanTecs, who bridge both the semiconductor and automotive worlds. The discussion will revolve around "Fail-Safe Electronics for Automotive," a topic of paramount importance in… Fail-safe Electronics for Automotive
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Join us at the TSMC 2023 China OIP Ecosystem Forum! China OIP Ecosystem Forum (In-Person Event) Date: November 15, 2023 (Wednesday) Time: 9:30a.m. - 5:45p.m. Venue: Shangri-La Nanjing Hotel 329 Zhongyang Road, Gulou District, Nanjing, Jiangsu Province, 210037 China China OIP Ecosystem Forum (Online VOD Event) Date: November 22, 2023 (Wednesday) Website link to be provided in November.… TSMC 2023 Open Innovation Platform Ecosystem Forum – China
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ASIP University Day: Domain-Specific Processor Design using ASIP Designer Application-specific instruction set processors (ASIPs) have established themselves as an important implementation option for modern SoCs, i.e. when standard processor IP cannot meet challenging application-specific requirements, and fixed hardware is not flexible enough. Heterogeneous multicore systems including ASIPs are now becoming more mainstream. Domains such as… ASIP University Day 2023 |
9 events,
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Silvaco UseRs Global Events (SURGE) bring together users, developers, and industry experts of the EDA, IP, and TCAD communities to understand new semiconductor technologies, innovative applications, and techniques for realizing advanced designs. Presentations A variety of presentations will cover semiconductor device simulation, circuit design and verification, and IP design. Roadmaps and exciting technology updates will… Silvaco UseRs Global Event (SURGE) 2023 – Korea
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Workshop on the Evolution of SystemC Standards: 16 November 2023 The eight SystemC Evolution Day is a full-day, technical workshop on the evolution of SystemC standards to advance the SystemC ecosystem. In several in-depth sessions, selected current and future standardization topics around SystemC will be discussed in order to accelerate their progress for inclusion in… SystemC Evolution Day 2023
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Elevate your success with osmosis 2023 Osmosis is about sharing success in using formal techniques to solve verification challenges, and networking with our R&D experts and other attendees. As such, we have put together the following conference program covering a wide range of formal verification topics – along with delivering sneak-previews of our future product… Formal Verification Conference: Osmosis 2023 |
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2 events,
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Silvaco UseRs Global Events (SURGE) bring together users, developers, and industry experts of the EDA, IP, and TCAD communities to understand new semiconductor technologies, innovative applications, and techniques for realizing advanced designs. Presentations A variety of presentations will cover semiconductor device simulation, circuit design and verification, and IP design. Roadmaps and exciting technology updates will… Silvaco UseRs Global Event (SURGE) 2023 – EMEA
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Designers face enormous challenges for low-power designs. Whether it is IoT at the edge, AI in the datacenter, robotics or ADAS, the demand for increased functionality in SoCs is rapidly outpacing the power budget. Power must be considered at every stage of chip design including performance, reliability and packaging. Waiting to address power until late… RTL Power Optimization: Applying Best Practices to Overcome Low-Power Design Challenges |
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1 event,
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Silvaco UseRs Global Events (SURGE) bring together users, developers, and industry experts of the EDA, IP, and TCAD communities to understand new semiconductor technologies, innovative applications, and techniques for realizing advanced designs. Presentations A variety of presentations will cover semiconductor device simulation, circuit design and verification, and IP design. Roadmaps and exciting technology updates will… Silvaco UseRs Global Event (SURGE) 2023 – Taiwan/Singapore |
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The FPGA Front Runners event will be hosted by Thales at their venue in Reading. The event will focus on “Security at System Level, and what security features we need in our FPGA to support this”. If you are interested in speaking at this event please email mike.bartley@techworks.org.uk Topics for talks: What is Security in FPGA-based… FPGA Frontrunner Meet & Greet |
3 events,
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Silvaco UseRs Global Events (SURGE) bring together users, developers, and industry experts of the EDA, IP, and TCAD communities to understand new semiconductor technologies, innovative applications, and techniques for realizing advanced designs. Presentations A variety of presentations will cover semiconductor device simulation, circuit design and verification, and IP design. Roadmaps and exciting technology updates will… Silvaco UseRs Global Event (SURGE) 2023 – Japan
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System-on-Chip (SoC) designs continue to grow in both size and complexity in order to meet the ever-growing performance and power demands associated with modern technology. To keep up with this fast-paced evolution, the corresponding design-for-test (DFT) logic required for manufacturing tests has also become more complex. Increasing transistor density, combined with a growing mix of… Making the Right Connections – Taking the Guess Work out of DFT Connectivity Validation
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Agenda (BST): Time Session Description Slides Videos 12.00 GMT Welcome and Introduction Mike Bartley,Tessolve 12.00 GMT Agnisys 12.30 GMT Imperas 12.45 GMT Breker 13.00 GMT Close About DVClub The principal goal of each DVCLUB meeting is to have fun while helping build the European verification community through regular educational and networking events. Attendance at DVClub Europe… Auto-generation of Verification Infrastructure for IP to SoC |
1 event,
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Synopsys Webinar – Part II In this 3-part Synopsys webinar series, we will present how hyperscale data centers are going through a paradigm shift with the advent of technologies like Artificial Intelligence (AI) and edge compute requiring hyperscale data centers to support exponential growth of data volume. This volume of network traffic demands an increase… CMOS Circuit Techniques for Wireline Transmitters Part II |
3 events,
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ANSYS’ VIRTUAL USER CONFERENCE FOR ELECTRONICS, SEMICONDUCTORS AND PHOTONICS DESIGNERS Join us for the IDEAS Digital Forum — a place to catch up on industry best practices and the latest semiconductor, electronic, and photonic design advances. IDEAS will explore future trends with keynotes from industry leaders and offer technical insights by expert chip designers from… Innovative Designs Enabled by Ansys Solutions – IDEAS 2023
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Wall-modeled large eddy simulations (WMLES) of complex vehicle geometries offer highly accurate results but can be challenging in terms of speed and cost. In this webinar, learn how to maximize the throughput of these simulations with Fidelity CharLES and how the solver’s GPU acceleration lowers the cost of using WMLES in engineering design. We will… Large Eddy CFD Simulation for Automotive Aerodynamics
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In this webinar Jeff DiCorpo & Matt Venn will delve into the latest ASIC developments, including the game-changing OpenFrame – a new Caravel version expanding your design possibilities by 50%. Topics Include: OpenFrame - a new version of Caravel that gives 50% more area GPIO configuration questions The new cocotb testing framework IPM - The… Latest Innovations and Updates in ASICs with Efabless |
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