Calendar of Events
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IP vendor SiFive has been at the forefront of RISC-V’s rapidly growing adoption across a wide array of markets and applications. In this joint presentation with Ansys, SiFive will describe how achieving maximum compute density - compute horsepower per mm2 and per mW (e.g SPECint2006/mm2) - has been a driving goal for SiFive’s portfolio of… SiFive Maximizes Compute Density With Its RISC-V Processor Cores
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STAC Summits bring together CTOs and other industry leaders responsible for solution architecture, infrastructure engineering, application development, machine learning/deep learning engineering, data engineering, and operational intelligence to discuss important technical challenges in trading and investment. |
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Abstract: Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series, we will present a step-by-step approach on how to architect a testbench - progressing from basic to advanced techniques. We will first use a simple DUT then go to a more… Advanced Testbench for a Simple DUT
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Increasingly complex automotive systems are driving the need for new and powerful E/E architectures, and new technology is emerging that offers a significant computational increase compared to previous generation SoCs. To deliver next-generation, differentiated software solutions, model-based design (MBD) workflows must be deployed to handle this new level of complexity. Code generation solutions that optimize… Accelerate Software Innovation Through Target-Optimized Code Generation and Virtual Prototypes |
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On 5-9th June, in Barcelona, RISC-V Summit Europe brings together developers, architects, technical decision and policy makers from across European RISC-V ecosystem. Attendees from academia, research, SMEs, industry and open source communities will gather to exchange knowledge, ideas, technologies, and research shaping the future of RISC-V computing. The event will include a single track of… RISC-V Summit Europe |
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Xcelium mixed-signal simulation enables teams to achieve digital simulation speeds of analog models and opens mixed-signal designs to advanced verification techniques typically applied within standard verification flows. Built on a SystemVerilog Real Number Modeling (RNM) foundation, Xcelium automates the signal integration of digital and RNM code to achieve digital simulation speeds for mixed-signal designs. This… Xcelium: The Key to Unlocking Unmatched Mixed-Signal Performance |
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VLSI Symposium is an international conference on semiconductor technology and circuits that offers an opportunity to interact and synergize on topics spanning the range from process technology to system-on-chip. We appreciate you to visit the VLSI symposium website. We also would like to invite you to join “2023 Symposium on VLSI technology and Circuits,” which… 2023 Symposium on VLSI Technology and Circuits 
IMS will be presented in-person, 11-16 June 2023 in San Diego, CA. IMS is the flagship event in a week dedicated to all things microwaves and RF. The week also includes the IEEE MTT-S Radio Frequency Integrated Circuits Symposium (RFIC) and the Automatic Radio Frequency Techniques Group (ARFTG). 2023 Sponsors |
5 events,
The PCI-SIG Developers Conference 2023 is returning to Santa Clara on June 13-14, 2023! Members of the PCI-SIG community including systems architects, designers, engineers, and engineering managers agree that this is an event you won’t want to miss. Overview The PCI-SIG Developers Conferences is a free event for our 900+ member companies that develop and bring… PCI-SIG Developers Conference 2023
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About This Webinar Engineers worldwide use Ansys HFSS software to design high-frequency, high-speed electronics found in communications systems, advanced driver assistance systems (ADAS), satellites, and internet-of-things (IoT) products. Ansys HFSS is a 3D electromagnetic (EM) simulation software for designing and simulating high-frequency electronic products such as antennas, antenna arrays, RF or microwave components, high-speed interconnects,… Run Ansys HFSS in the Cloud with AWS to Boost Simulation
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Fueled by the recent adoption by leading smartphone brands, the UWB wireless technology is enjoying an explosive growth in market interest and applications. In automotive, UWB is already the de-facto choice for Digital Keys in the premium segment. The deployment of UWB anchor points in modern car creates a cost-effective platform for offering advanced in-cabin radar,… Driving Forward with UWB Radar: Enhancing Child Safety in Automotive |
6 events,
Dealing with Uncertainty The global economy is sending mixed messages, and with every new data release comes a new batch of upbeat or defeatist headlines. Uncertainty remains if inflation is fully under control and how quickly economic growth will pick up strongly again. On one side the labor market seems healthier than it’s been in… GSA 2023 European Executive Forum
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Verifying an SoC is an extremely complex process that requires agile turnaround, constant control feedback, and flexibility to adapt to evolving project needs. Coverage is an efficient metric for the number of potential bugs found and needs to be tracked at each stage of the project. The verification process starts from defining the verification goals,… Verify Your SoC Design Efficiently from Planning to Coverage Closure using Synopsys Verification Family
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Whether you are developing Systems-on-Chip (SoCs) for mobile and wearables, automotive, aerospace, defense, data centers, or entertainment, securing your proprietary data and customers’ information is critical to your company’s long-term success. Hackers can exploit vulnerabilities in these systems — at the network, system, device, or chip levels. As SoC designs get more complex, this 30-minute… Microelectronics Design Security: Better with Formal Methods |
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As the electronics industry's largest user conference, SNUG Taiwan is dedicated to demonstrating the state-of-the-art innovations from the chip design community around the globe. This year, we are excited to announce that the SNUG Taiwan in-person event is back! SNUG Taiwan continues to foster the link between Synopsys’ tool users and technical experts so they… SNUG Taiwan 2023
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The webinar focuses on the simulation-driven optimization of electronics, Integrated Circuits applications to achieve a six-sigma level of quality. Electronics are part of our daily life, with innovative and connected transportation, buildings, and communications. However, the design of electronic devices is a complex process, and achieving a six-sigma level of quality is a significant challenge.… Designing for Six Sigma: Electronics Simulation Powered by Parametric Variation
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RISC-V Day Tokyo 2023 Summer Conference is Japan’s largest RISC-V real event. RISC-V Day Tokyo 2023 Summer Conference will be held on June 20, 2023 (Tuesday) from 9:00 to 20:30 Japan time (JST). A real presentation will be held at Ito Hall ( B2 floor of Ito International Research Center, the University of Tokyo ).… RISC-V Days Tokyo 2023 Summer |
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The problem of optimization is a long-standing one in the field of design. For years, the most conventional approach was the brute-force method of running parametric sweeps on the design space. However, as systems become more complex and the number of parameters increases, the computational resource and time cost becomes unsustainable. With the Cadence Optimality… Applying AI/ML Technology for Rapid Design Optimization
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Achieve Out-of-the-Box Equivalence Checking with Synopsys Formality ML-driven Distributed Processing
Achieve Out-of-the-Box Equivalence Checking with Synopsys Formality ML-driven Distributed Processing
When designers synthesize chip designs with aggressive PPA targets, the expectation and goal is to be able to complete verification with minimal effort and a fast turn-around-time. Synopsys Design Compiler and Fusion Compiler offer a broad spectrum of optimization techniques such as retiming, multibit banking and advanced data-path optimizations, though these techniques can end up… Achieve Out-of-the-Box Equivalence Checking with Synopsys Formality ML-driven Distributed Processing |
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The Verification Futures conference provides a unique blend of conference presentations, exhibitions, training and industry networking sessions dedicated to discussing the challenges faced in hardware and software verification. Verification Futures provides a unique opportunity for end-users to define their current and future verification challenges and collaborate with the vendors to create solutions. It also provides… Verification Futures 2023 UK
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The architecture and heterogeneous integration capability of 3D-IC (three-dimensional integrated circuits) offer many benefits. The latest configuration methods, CoWoS (Chip On Wafer on Substrate) and WoW (Wafer on Wafer) from TSMC, provide advantages by significantly reducing the interconnect length and signal power loss. These new technologies have introduced the need for innovative ways to solve… Design and Analysis of Multi-Die & 3D-IC Systems
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The Design & Verification Conference & Exhibition is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits. The focus of this highly technical conference is on the practical aspects of these technologies and their use in leading-edge projects to encourage attendees… DVCon Japan 2023 |
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In the world of formal verification, abstractions along with design reductions, help reduce the state space and make it easier for formal to converge on its proofs. In this webinar Doulos Senior Member Technical Staff, Doug Smith will explore the process of abstraction, safe design reductions, and when to use them. Doug will show practical… Dealing with Complexity in Formal through Abstraction and Reduction |
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The SEMI 3D & Systems Summit this year is dedicated to Smarter Systems through Heterogeneous Integration. The semiconductor industry has had several changes in market, products, and tech advancements brought by disruptive technologies and Moore's Law plateauing. Therefore, continued developments and innovation are essential to growing the business. Industry experts will share their insights into… 3D & Systems Summit 
FOCUS The European Nanoelectronics Applications, Design & Technology Conference will focus on electronic components, electronic system design, design automation, and manufacturing topics related to micro- and nanoelectronics, which are critical to success for many European companies. Exhaustive research and development in this area have been supported by EUREKA, Horizon Europe, and local governments in recent… European Nanoelectronics Applications Design and Technology Conference |
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Day 1 June 27th, 2023 12:00 - 1:00pm PDT Networking Lunch & Registration 1:00 - 1:05pm PDT Opening Jinman Han EVP, Head of DSA Office, Samsung Electronics 1:05 - 1:20pm PDT Samsung Keynote Siyoung Choi President and GM, Foundry Business, Samsung Electronics 1:20 - 1:35pm PDT An Energy Efficient Future of AI Joe Macri SVP, CTO… SFF & SAFE™ Forum 2023 San Jose, CA
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RISC-V is revolutionizing the future of Artificial Intelligence (AI) in industries such as automotive, data center, communications, and IoT. Its open-source instruction set architecture (ISA) provides higher performance, lower power, and compact silicon footprint, features highly desired by these industry segments. RISC-V has gained rapid widespread adoption due to its compact instruction set and extensibility.… 2023 Andes RISC-V CON
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Verisium Debug offers comprehensive debugging capabilities. From RTL, UVM testbench to UPF low-power designs, users can use the Cadence unified debugging platform for debugging. In this webinar, users will learn about the available features in Verisium Debug for UPF power-aware designs and using the unique capabilities to visualize and debug UPF low-power designs. What you… Verisium Debug for UPF Low Power Design |
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The aim of the MIXDES conference is to provide an annual Central-European forum for the presentation and discussion of recent advances in design, modeling, simulation, testing and manufacturing in various areas such as micro- and nanoelectronics, semiconductors, sensors, actuators and power devices. The MIXDES conference papers will be submitted for inclusion into IEEE Xplore, subject… 30th MIXDES Conference
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Chiplets are emerging as a new way of building IC systems via heterogeneous integration, and Universal Chip Interconnect Express (UCIe) is one of the standards defining the interconnects among chiplets. This webinar presents the SystemVerilog models of a Universal Chiplet Interconnect Express (UCIe) interface, including both the analog circuits in the electrical layer and digital… UCIe PHY Modeling and Simulation with XMODEL |
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Japan Technology Symposium Date Friday, June 30 Time 9:30 a.m. - 5:20 p.m. Venue The Yokohama Bay Hotel Tokyu 2-3-7, Minatomirai, Nishi-ku, Yokohama 220-8543 Registration will be closed on 6/21. Seats are limited. VoD (Video on Demand) will be available starting from 7/21. Registration will close on 7/12. Get the latest on: TSMC's smartphone, HPC,… TSMC 2023 Technology Symposium – Japan |
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